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[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_regs.v] - Diff between revs 2 and 9

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Rev 2 Rev 9
Line 56... Line 56...
  input                       bus_clk,      // Control register bus clock
  input                       bus_clk,      // Control register bus clock
  input                       async_rst_b,  // Async reset signal
  input                       async_rst_b,  // Async reset signal
  input                       sync_reset,   // Syncronous reset signal
  input                       sync_reset,   // Syncronous reset signal
  input                       cop_flag,     // COP Rollover Flag
  input                       cop_flag,     // COP Rollover Flag
  input          [DWIDTH-1:0] write_bus,    // Write Data Bus
  input          [DWIDTH-1:0] write_bus,    // Write Data Bus
  input                [ 4:0] write_regs,   // Write Register strobes
  input                [ 4:0] write_regs    // Write Register strobes
  input                       cnt_flag_o    // Counter Rollover Flag 
 
  );
  );
 
 
 
 
  // registers
  // registers
  reg         service_cop; // Service register to reload COP Timeout Counter
  reg         service_cop; // Service register to reload COP Timeout Counter

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