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-- Company:
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--
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-- File: cp_Toggle.vhd
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--
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-- Description:
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-- projet copyblaze
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-- Toggle horloge clock (divisor by 2)
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--
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-- File history:
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-- v1.0: 07/10/11: Creation
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-- v2.0: 25/10/11: Add Freeze Management
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--
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-- Targeted device: ProAsic A3P250 VQFP100
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-- Author: AbdAllah Meziti
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Usefull_Pkg.all; -- Usefull Package
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-- Entity: cp_Toggle
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--
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-- Description:
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--
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-- REMARQUE:
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--
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--
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-- History:
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-- 07/10/11 AM: Creation
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-- ---------------------
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-- xx/xx/xx AM:
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--
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--------------------------------------------------------------------------------
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entity cp_Toggle is
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port (
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--------------------------------------------------------------------------------
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-- Signaux Systeme
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--------------------------------------------------------------------------------
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Clk_i : in std_ulogic; -- signal d'horloge générale
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Rst_i_n : in std_ulogic; -- signal de reset générale
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--------------------------------------------------------------------------------
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-- Signaux Fonctionels
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--------------------------------------------------------------------------------
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Freeze_i : in std_ulogic;
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Phase1_o : out std_ulogic;
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Phase2_o : out std_ulogic
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);
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end cp_Toggle;
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-- Architecture: RTL
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-- of entity : cp_Toggle
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--------------------------------------------------------------------------------
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architecture rtl of cp_Toggle is
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--------------------------------------------------------------------------------
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-- Définition des fonctions
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--------------------------------------------------------------------------------
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type States_TYPE is
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(
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S_NORMAL , --
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S_FREEZE -- for external "Freeze processor" signal
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);
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--------------------------------------------------------------------------------
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-- Définition des constantes
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Définition des signaux interne
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--------------------------------------------------------------------------------
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signal iFSM_State : States_TYPE; -- Signal de la machine d'état
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signal iPhase1 : std_ulogic;
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signal iPhase2 : std_ulogic;
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signal iPhase1Out : std_ulogic;
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signal iPhase2Out : std_ulogic;
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--------------------------------------------------------------------------------
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-- Déclaration des composants
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--------------------------------------------------------------------------------
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begin
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--------------------------------------------------------------------------------
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-- Process : Phase_Proc
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-- Description: generate the Phase1 and Phase2 of the processor
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--------------------------------------------------------------------------------
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Phase_Proc : process(Rst_i_n, Clk_i)
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begin
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if ( Rst_i_n = '0' ) then
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iPhase1 <= '0';
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iPhase2 <= '0';
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elsif ( rising_edge(Clk_i) ) then
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iPhase1 <= not( iPhase1 );
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iPhase2 <= iPhase1;
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end if;
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end process Phase_Proc;
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--------------------------------------------------------------------------------
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-- Process : Freeze_Proc
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-- Description: if Freeze_i signal is active, then the processor exectution is freezed (stoped)
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--------------------------------------------------------------------------------
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Freeze_Proc : process(Rst_i_n, Clk_i)
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begin
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if ( Rst_i_n = '0' ) then
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iFSM_State <= S_NORMAL;
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elsif ( rising_edge(Clk_i) ) then
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case iFSM_State is
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when S_NORMAL =>
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if ( ( iPhase2 = '1' ) and (Freeze_i = '1') ) then
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iFSM_State <= S_FREEZE;
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end if;
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when S_FREEZE =>
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if ( ( iPhase2 = '1' ) and (Freeze_i = '0') ) then
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iFSM_State <= S_NORMAL;
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end if;
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end case;
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end if;
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end process Freeze_Proc;
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with iFSM_State select
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iPhase1Out <= iPhase1 when S_NORMAL,
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'0' when S_FREEZE, -- Phase 1 to 0
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'0' when others;
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with iFSM_State select
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iPhase2Out <= iPhase2 when S_NORMAL,
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'0' when S_FREEZE, -- Phase 2 to 0
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'0' when others;
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Phase1_o <= iPhase1Out;
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Phase2_o <= iPhase2Out;
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end rtl;
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No newline at end of file
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