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-----------------------------------------------------------------------------
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-- Wishbone GPIO ------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.ALL;
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entity wb_gpio is
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- Wishbone bus
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wb_adr_i : in std_logic_vector(31 downto 0);
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wb_dat_i : in std_logic_vector(31 downto 0);
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wb_dat_o : out std_logic_vector(31 downto 0);
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wb_sel_i : in std_logic_vector( 3 downto 0);
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wb_cyc_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_ack_o : out std_logic;
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wb_we_i : in std_logic;
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-- I/O ports
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iport : in std_logic_vector(31 downto 0);
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oport : out std_logic_vector(31 downto 0) );
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end wb_gpio;
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-----------------------------------------------------------------------------
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-- Implementation -----------------------------------------------------------
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architecture rtl of wb_gpio is
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signal wbactive : std_logic;
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signal oport_reg : std_logic_vector(31 downto 0);
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signal iport_reg : std_logic_vector(31 downto 0);
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begin
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oport <= oport_reg;
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-- synchronize incoming signals (anti-meta-state)
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syncproc: process(clk) is
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begin
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if clk'event and clk='1' then
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iport_reg <= iport;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Wishbone handling --------------------------------------------------------
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wb_ack_o <= wb_stb_i and wb_cyc_i;
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wb_dat_o <= iport_reg when wb_stb_i='1' and wb_cyc_i='1' and wb_adr_i(3 downto 0)=x"0" else
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oport_reg when wb_stb_i='1' and wb_cyc_i='1' and wb_adr_i(3 downto 0)=x"4" else
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(others => '-');
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writeproc: process (reset, clk) is
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variable val : std_logic_vector(31 downto 0);
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begin
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if reset='1' then
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oport_reg <= (others => '0');
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elsif clk'event and clk='1' then
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if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
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-- decode WB_SEL_I --
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if wb_sel_i(3)='1' then
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val(31 downto 24) := wb_dat_i(31 downto 24);
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end if;
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if wb_sel_i(2)='1' then
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val(23 downto 16) := wb_dat_i(23 downto 16);
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end if;
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if wb_sel_i(1)='1' then
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val(15 downto 8) := wb_dat_i(15 downto 8);
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end if;
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if wb_sel_i(0)='1' then
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val( 7 downto 0) := wb_dat_i( 7 downto 0);
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end if;
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-- decode WB_ADR_I --
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if wb_adr_i(3 downto 0)=x"4" then
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oport_reg <= val;
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end if;
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end if;
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end if;
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end process;
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end rtl;
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