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-----------------------------------------------------------------------------
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-- On-chip logic analyzer with wishbone bus for control and data export.
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-- Waveforms are stored in local BlockRAM which size (depth) can be
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-- configured via a generic.
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--
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-- (c) 2006 by Joerg Bornschein (jb@capsec.org)
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-- All files under GPLv2
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-----------------------------------------------------------------------------
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-- Wishbone LogicAnalyzer ---------------------------------------------------
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entity wb_scope is
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generic (
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depth : natural := 4096 );
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- 32 Bit Wishbone Slave
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wb_adr_i : in std_logic_vector(31 downto 0);
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wb_dat_i : in std_logic_vector(31 downto 0);
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wb_dat_o : out std_logic_vector(31 downto 0);
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wb_sel_i : in std_logic_vector( 3 downto 0);
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wb_cyc_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_ack_o : out std_logic;
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wb_we_i : in std_logic;
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wb_irq_o : out std_logic;
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-- I/O ports
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probe : in std_logic_vector(31 downto 0) );
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end wb_scope;
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-----------------------------------------------------------------------------
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-- 0x00000 Status Register:
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-- +-----------------+-------+-------+-------+
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-- | ... 0 ... | SDONE | IRQEN | SPLEN |
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-- +-----------------+-------+-------+-------+
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--
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-- 0x00004 Sample Pointer -- (0x0000 : 0xFFFF)
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-- 0x00008 Sample Counter -- (Stop when 0)
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-- 0x00010 Channel 0
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-- 0x00011 Channel 1
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-- 0x00012 Channel 2
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-- 0x00013 Channel 3
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-- 0x1???? Data
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Implementation -----------------------------------------------------------
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architecture rtl of wb_scope is
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-----------------------------------------------------------------------------
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-- Components ---------------------------------------------------------------
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component bram_dp is
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generic (
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depth : natural );
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- Port 1
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we1 : in std_logic;
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addr1 : in std_logic_vector(11 downto 0);
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wdata1 : in std_logic_vector(31 downto 0);
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-- Port 2
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oe2 : in std_logic;
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addr2 : in std_logic_vector(11 downto 0);
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rdata2 : out std_logic_vector(31 downto 0) );
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end component;
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component mux32 is
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port (
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input : in std_logic_vector(31 downto 0);
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output : out std_logic;
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sel : in std_logic_vector(4 downto 0) );
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end component;
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-----------------------------------------------------------------------------
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-- Local Signals ------------------------------------------------------------
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constant ZEROS : std_logic_vector(31 downto 0) := (others => '0');
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signal wbactive : std_logic;
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signal status_reg : std_logic_vector(31 downto 0);
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signal sp : std_logic_vector(15 downto 0); -- SamplePointer
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signal sc : std_logic_vector(15 downto 0); -- SampleCounter
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signal spen : std_logic; -- Sample Enable
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signal irqen : std_logic; -- IRQ Enable
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signal sdone : std_logic; -- Sampling Done
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signal sreg : std_logic_vector(27 downto 0); -- sample register
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signal chan : std_logic_vector( 3 downto 0); -- actual data to be sampled
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signal probe_b : std_logic_vector(31 downto 0); -- buffered probes
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signal csel0 : std_logic_vector(4 downto 0);
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signal csel1 : std_logic_vector(4 downto 0);
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signal csel2 : std_logic_vector(4 downto 0);
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signal csel3 : std_logic_vector(4 downto 0);
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signal we1 : std_logic;
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signal addr1 : std_logic_vector(11 downto 0);
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signal wdata1: std_logic_vector(31 downto 0);
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signal oe2 : std_logic;
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signal addr2 : std_logic_vector(11 downto 0);
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signal rdata2: std_logic_vector(31 downto 0);
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signal ram_ack : std_logic;
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begin
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-- Sample RAM ---------------------------------------------------------------
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ram0: bram_dp
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generic map (
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depth => depth )
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port map (
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clk => clk,
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reset => reset,
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-- Port 1 (probe & sample engine (write only))
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we1 => we1,
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addr1 => addr1,
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wdata1 => wdata1,
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-- Port 2 (Wishbone Access (read only))
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oe2 => oe2,
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addr2 => addr2,
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rdata2 => rdata2 );
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wbactive <= wb_stb_i and wb_cyc_i;
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addr2 <= wb_adr_i(13 downto 2);
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oe2 <= '1' when wbactive='1' and wb_adr_i(19 downto 16)=x"1" else
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'0';
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wb_dat_o <= status_reg when wbactive='1' and wb_adr_i(19 downto 16)=x"0" and wb_adr_i( 7 downto 0)=x"00" else
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ZEROS(31 downto 16) & sp when wbactive='1' and wb_adr_i(19 downto 16)=x"0" and wb_adr_i( 7 downto 0)=x"04" else
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ZEROS(31 downto 16) & sc when wbactive='1' and wb_adr_i(19 downto 16)=x"0" and wb_adr_i( 7 downto 0)=x"08" else
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ZEROS(2 downto 0)&csel3 &
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ZEROS(2 downto 0)&csel2 &
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ZEROS(2 downto 0)&csel1 &
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ZEROS(2 downto 0)&csel0 when wbactive='1' and wb_adr_i(19 downto 16)=x"0" and wb_adr_i( 7 downto 0)=x"10" else
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rdata2 when wbactive='1' and wb_adr_i(19 downto 16)=x"1" else
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(others => '-');
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wb_ack_o <= wbactive and ram_ack when wb_adr_i(19 downto 16)=x"1" else
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wbactive;
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wb_irq_o <= sdone and irqen;
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status_reg <= ZEROS(31 downto 3) & sdone & irqen & spen;
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wbproc: process(reset, clk) is
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variable scv : unsigned(15 downto 0);
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variable spv : unsigned(15 downto 0);
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begin
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if reset='1' then
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spen <= '0';
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irqen <= '0';
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sdone <= '0';
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sp <= (others => '0');
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sc <= (others => '0');
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csel0 <= (others => '0');
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csel1 <= (others => '0');
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csel2 <= (others => '0');
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csel3 <= (others => '0');
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sreg <= (others => '0');
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we1 <= '0';
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ram_ack <= '0';
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elsif clk'event and clk='1' then
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-- Sample Data
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if spen='1' then
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-- sampling done?
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if sc=ZEROS(15 downto 0) then
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spen <= '0';
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sdone <= '1';
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end if;
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-- sample into sreg
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if sp(2 downto 0)="111" then
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addr1 <= sp(14 downto 3);
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wdata1 <= sreg & chan;
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we1 <= '1';
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else
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sreg <= sreg(23 downto 0) & chan;
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we1 <= '0';
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end if;
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-- increase pointer; decrease counter
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scv := unsigned(sc);
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scv := scv - 1;
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sc <= std_logic_vector(scv);
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spv := unsigned(sp);
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spv := spv + 1;
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sp <= std_logic_vector(spv);
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end if;
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-- WB register write request
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if wbactive='1' and wb_we_i='1' and wb_adr_i(19 downto 16)=x"0" then
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if wb_adr_i(7 downto 0)=x"00" then -- StatusRegister
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spen <= wb_dat_i(0);
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irqen <= wb_dat_i(1);
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sdone <= '0';
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end if;
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if wb_adr_i(7 downto 0)=x"04" then -- SamplePointer
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sp <= wb_dat_i(15 downto 0);
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end if;
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if wb_adr_i(7 downto 0)=x"08" then -- SampleCounter
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sc <= wb_dat_i(15 downto 0);
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end if;
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if wb_adr_i(7 downto 0)=x"10" then -- Channel Sel
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if wb_sel_i(0)='1' then
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csel3 <= wb_dat_i( 4 downto 0);
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end if;
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if wb_sel_i(1)='1' then
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csel2 <= wb_dat_i(12 downto 8);
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end if;
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if wb_sel_i(2)='1' then
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csel1 <= wb_dat_i(20 downto 16);
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end if;
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if wb_sel_i(3)='1' then
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csel0 <= wb_dat_i(28 downto 24);
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end if;
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end if;
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end if;
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-- Buffer read request
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if wbactive='1' and wb_adr_i(19 downto 16)=x"1" then
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ram_ack <= '1' and not ram_ack;
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else
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ram_ack <= '0';
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end if;
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end if;
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end process;
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-- Probe buffering and muxing -----------------------------------------------
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bufproc: process(clk, reset) is -- buffer probes BEFORE mux (timing)
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begin
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if reset='1' then
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probe_b <= (others => '0');
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elsif clk'event and clk='1' then
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probe_b <= probe;
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end if;
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end process;
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mux0: mux32 -- Channel 0
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port map (
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input => probe_b,
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output => chan(0),
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sel => csel0 );
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mux1: mux32 -- Channel 1
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port map (
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input => probe_b,
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output => chan(1),
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sel => csel1 );
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mux2: mux32 -- Channel 2
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port map (
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input => probe_b,
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output => chan(2),
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sel => csel2 );
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mux3: mux32 -- Channel 3
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port map (
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input => probe_b,
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output => chan(3),
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sel => csel3 );
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end rtl;
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No newline at end of file
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No newline at end of file
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