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-----------------------------------------------------------------------------
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-- Wishbone TIMER -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity wb_timer is
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- Wishbone bus
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wb_adr_i : in std_logic_vector(31 downto 0);
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wb_dat_i : in std_logic_vector(31 downto 0);
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wb_dat_o : out std_logic_vector(31 downto 0);
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wb_sel_i : in std_logic_vector( 3 downto 0);
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wb_cyc_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_ack_o : out std_logic;
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wb_we_i : in std_logic;
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wb_irq0_o: out std_logic;
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wb_irq1_o: out std_logic );
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end wb_timer;
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-----------------------------------------------------------------------------
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-- 0x00: TCR0 Timer Control and Status Register
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-- 0x04: COMPARE0
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-- 0x08: COUNTER0
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-- 0x0C: TCR1
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-- 0x10: COMPARE1
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-- 0x14: COUNTER1
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--
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-- TCRx:
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--
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-- +-----------------------------------+-----+-----+--------+-------+
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-- | ZEROs (31 downto 4) | en0 | ar0 | irq0en | trig0 |
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-- +-----------------------------------+-----+-----+--------+-------+
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--
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-----------------------------------------------------------------------------
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-- Implementation -----------------------------------------------------------
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architecture rtl of wb_timer is
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signal wbactive : std_logic;
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signal counter0 : unsigned(31 downto 0);
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signal counter1 : unsigned(31 downto 0);
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signal compare0 : unsigned(31 downto 0);
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signal compare1 : unsigned(31 downto 0);
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signal en0, en1 : std_logic; -- Enable counter
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signal ar0, ar1 : std_logic; -- Auto Reload
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signal trig0, trig1 : std_logic; -- Triggered
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signal irq0en, irq1en: std_logic; -- Enable Interrupt
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signal tcr0, tcr1 : std_logic_vector(31 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Wishbone handling --------------------------------------------------------
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wbactive <= wb_stb_i and wb_cyc_i;
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wb_ack_o <= wbactive;
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wb_dat_o <= tcr0 when wbactive='1' and wb_adr_i(7 downto 0)=x"00" else
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std_logic_vector(compare0) when wbactive='1' and wb_adr_i(7 downto 0)=x"04" else
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std_logic_vector(counter0) when wbactive='1' and wb_adr_i(7 downto 0)=x"08" else
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tcr1 when wbactive='1' and wb_adr_i(7 downto 0)=x"0C" else
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std_logic_vector(compare1) when wbactive='1' and wb_adr_i(7 downto 0)=x"10" else
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std_logic_vector(counter1) when wbactive='1' and wb_adr_i(7 downto 0)=x"14" else
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(others => '-');
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wb_irq0_o <= trig0 and irq0en;
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wb_irq1_o <= trig1 and irq1en;
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tcr0 <= "0000000000000000000000000000" & en0 & ar0 & irq0en & trig0;
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tcr1 <= "0000000000000000000000000000" & en1 & ar1 & irq1en & trig1;
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timerproc: process (reset, clk) is
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variable val : std_logic_vector(31 downto 0);
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begin
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if reset='1' then
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en0 <= '0'; -- enable
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en1 <= '0';
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ar0 <= '0'; -- auto reload
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ar1 <= '0';
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trig0 <= '0'; -- triggered
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trig1 <= '0';
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irq0en <= '0'; -- IRQ enable
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irq1en <= '0';
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compare0 <= TO_UNSIGNED(0, 32); -- compare
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compare1 <= TO_UNSIGNED(0, 32);
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counter0 <= TO_UNSIGNED(0, 32); -- actual counter
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counter1 <= TO_UNSIGNED(0, 32);
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elsif clk'event and clk='1' then
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-- Reset trigX on TCR access --------------------------------
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if wbactive='1' and wb_adr_i(7 downto 0)=x"00" then
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trig0 <= '0';
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end if;
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if wbactive='1' and wb_adr_i(7 downto 0)=x"0C" then
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trig1 <= '0';
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end if;
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-- WB write register ----------------------------------------
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if wbactive='1' and wb_we_i='1' then
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-- decode WB_SEL_I --
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if wb_sel_i(3)='1' then
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val(31 downto 24) := wb_dat_i(31 downto 24);
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end if;
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if wb_sel_i(2)='1' then
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val(23 downto 16) := wb_dat_i(23 downto 16);
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end if;
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if wb_sel_i(1)='1' then
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val(15 downto 8) := wb_dat_i(15 downto 8);
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end if;
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if wb_sel_i(0)='1' then
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val( 7 downto 0) := wb_dat_i( 7 downto 0);
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end if;
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-- decode WB_ADR_I --
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if wb_adr_i(7 downto 0)=x"00" then
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en0 <= val(3);
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ar0 <= val(2);
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irq0en <= val(1);
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elsif wb_adr_i(7 downto 0)=x"04" then
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compare0 <= unsigned(val);
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elsif wb_adr_i(7 downto 0)=x"08" then
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counter0 <= unsigned(val);
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elsif wb_adr_i(7 downto 0)=x"0C" then
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en1 <= val(3);
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ar1 <= val(2);
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irq1en <= val(1);
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elsif wb_adr_i(7 downto 0)=x"10" then
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compare1 <= unsigned(val);
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elsif wb_adr_i(7 downto 0)=x"14" then
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counter1 <= unsigned(val);
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end if;
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end if;
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-- timer0 ---------------------------------------------------
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if en0='1' then
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if counter0 = compare0 then
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trig0 <= '1';
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if ar0='1' then
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counter0 <= to_unsigned(1, 32);
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else
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en0 <= '0';
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end if;
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else
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counter0 <= counter0 + 1;
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end if;
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end if;
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-- timer1 ---------------------------------------------------
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if en1='1' then
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if counter1 = compare1 then
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trig1 <= '1';
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if ar1='1' then
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counter1 <= to_unsigned(1, 32);
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else
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en1 <= '0';
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end if;
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else
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counter1 <= counter1 + 1;
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end if;
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end if;
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end if;
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end process;
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end rtl;
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