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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-----------------------------------------------------------------------------
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-- UART ---------------------------------------------------------------------
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entity myuart is
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port (
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clk : in std_ulogic;
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reset : in std_ulogic;
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--
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divisor : in std_ulogic_vector(15 downto 0);
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txdata : in std_ulogic_vector( 7 downto 0);
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rxdata : out std_ulogic_vector( 7 downto 0);
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wr : in std_ulogic;
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rd : in std_ulogic;
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tx_avail : out std_ulogic;
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tx_busy : out std_ulogic;
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rx_avail : out std_ulogic;
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rx_full : out std_ulogic;
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rx_error : out std_ulogic;
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--
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uart_rxd : in std_ulogic;
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uart_txd : out std_ulogic );
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end myuart;
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-----------------------------------------------------------------------------
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-- implementation -----------------------------------------------------------
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architecture rtl of myuart is
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-----------------------------------------------------------------------------
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-- component declarations ---------------------------------------------------
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component uart_rx is
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port (
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clk : in std_ulogic;
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reset : in std_ulogic;
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--
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divisor : in std_ulogic_vector(15 downto 0);
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dout : out std_ulogic_vector(7 downto 0);
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avail : out std_ulogic;
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error : out std_ulogic;
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clear : in std_ulogic;
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--
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rxd : in std_ulogic );
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end component;
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component uart_tx is
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port (
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clk : in std_ulogic;
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reset : in std_ulogic;
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--
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divisor : in std_ulogic_vector(15 downto 0);
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din : in std_ulogic_vector(7 downto 0);
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wr : in std_ulogic;
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busy : out std_ulogic;
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--
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txd : out std_ulogic );
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end component;
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-----------------------------------------------------------------------------
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-- local signals ------------------------------------------------------------
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signal utx_busy : std_ulogic;
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signal utx_wr : std_ulogic;
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signal urx_dout : std_ulogic_vector(7 downto 0);
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signal urx_avail : std_ulogic;
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signal urx_clear : std_ulogic;
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signal urx_error : std_ulogic;
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signal txbuf : std_ulogic_vector(7 downto 0);
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signal txbuf_full : std_ulogic;
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signal rxbuf : std_ulogic_vector(7 downto 0);
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signal rxbuf_full : std_ulogic;
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begin
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iotxproc: process(clk) is
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begin
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if clk'event and clk='1' then
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if reset='1' then
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utx_wr <= '0';
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txbuf_full <= '0';
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urx_clear <= '0';
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rxbuf_full <= '0';
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else
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-- TX Buffer Logic
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if wr='1' and not txbuf_full='1' then
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txbuf <= txdata;
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txbuf_full <= '1';
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end if;
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if txbuf_full='1' and utx_busy='0' then
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utx_wr <= '1';
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txbuf_full <= '0';
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else
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utx_wr <= '0';
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end if;
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-- RX Buffer Logic
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if rd='1' then
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rxbuf_full <= '0';
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end if;
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if urx_avail='1' and rxbuf_full='0' then
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rxbuf <= urx_dout;
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rxbuf_full <= '1';
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urx_clear <= '1';
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else
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urx_clear <= '0';
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end if;
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end if;
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end if;
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end process;
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rxdata <= rxbuf;
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rx_avail <= rxbuf_full and not rd;
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rx_full <= rxbuf_full and urx_avail and not rd;
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rx_error <= urx_error;
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tx_busy <= utx_busy or txbuf_full; -- or wr;
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tx_avail <= not txbuf_full;
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-- Instantiate RX and TX engine
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uart_rx0: uart_rx
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port map (
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clk => clk,
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reset => reset,
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--
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divisor => divisor,
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dout => urx_dout,
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avail => urx_avail,
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error => urx_error,
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clear => urx_clear,
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--
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rxd => uart_rxd );
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uart_tx0: uart_tx
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port map (
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clk => clk,
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reset => reset,
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--
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divisor => divisor,
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din => txbuf,
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wr => utx_wr,
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busy => utx_busy,
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--
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txd => uart_txd );
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end rtl;
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