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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-----------------------------------------------------------------------------
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-- UART Receiver ------------------------------------------------------------
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entity uart_rx is
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port (
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clk : in std_ulogic;
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reset : in std_ulogic;
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--
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divisor : in std_ulogic_vector(15 downto 0);
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dout : out std_ulogic_vector( 7 downto 0);
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avail : out std_ulogic;
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error : out std_ulogic;
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clear : in std_ulogic;
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--
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rxd : in std_ulogic );
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end uart_rx;
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-----------------------------------------------------------------------------
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-- Implemenattion -----------------------------------------------------------
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architecture rtl of uart_rx is
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-- Signals
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signal bitcount : integer range 0 to 10;
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signal count : unsigned(15 downto 0);
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signal shiftreg : std_ulogic_vector(7 downto 0);
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signal rxh : std_ulogic_vector(2 downto 0);
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signal rxd2 : std_ulogic;
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begin
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proc: process(clk, reset) is
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begin
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if clk'event and clk='1' then
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if reset='1' then
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count <= (others => '0');
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bitcount <= 0;
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error <= '0';
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avail <= '0';
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else
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if clear='1' then
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error <= '0';
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avail <= '0';
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end if;
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if count/=0 then
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count <= count - 1;
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else
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if bitcount=0 then -- wait for startbit
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if rxd2='0' then -- FOUND
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count <= unsigned("0" & divisor(15 downto 1) );
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bitcount <= bitcount + 1;
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end if;
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elsif bitcount=1 then -- sample mid of startbit
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if rxd2='0' then -- OK
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count <= unsigned(divisor);
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bitcount <= bitcount + 1;
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shiftreg <= "00000000";
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else -- ERROR
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error <= '1';
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bitcount <= 0;
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end if;
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elsif bitcount=10 then -- stopbit
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-- if rxd2='1' then -- OK
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bitcount <= 0;
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dout <= shiftreg;
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avail <= '1';
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-- else -- ERROR
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-- error <= '1';
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-- end if;
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else
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shiftreg(6 downto 0) <= shiftreg(7 downto 1);
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shiftreg(7) <= rxd2;
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count <= unsigned(divisor);
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bitcount <= bitcount + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Sync incoming RXD (anti metastable) --------------------------------------
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syncproc: process(reset, clk) is
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begin
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if reset='1' then
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rxh <= (others => '1');
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rxd2 <= '1';
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elsif clk'event and clk='1' then
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rxh <= rxh(1 downto 0) & rxd;
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if rxh="111" then
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rxd2 <= '1';
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elsif rxh="000" then
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rxd2 <= '0';
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end if;
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end if;
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end process;
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end rtl;
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