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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-----------------------------------------------------------------------------
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-- UART Transmitter ---------------------------------------------------------
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entity uart_tx is
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port (
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clk : in std_ulogic;
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reset : in std_ulogic;
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--
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divisor : in std_ulogic_vector(15 downto 0);
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din : in std_ulogic_vector( 7 downto 0);
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wr : in std_ulogic;
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busy : out std_ulogic;
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--
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txd : out std_ulogic );
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end uart_tx;
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-----------------------------------------------------------------------------
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-- Implemenattion -----------------------------------------------------------
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architecture rtl of uart_tx is
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-- Signals
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signal bitcount : integer range 0 to 10;
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signal count : unsigned(15 downto 0);
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signal shiftreg : std_ulogic_vector(7 downto 0);
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begin
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proc: process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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count <= (others => '0');
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bitcount <= 0;
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busy <= '0';
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txd <= '1';
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else
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if count/=0 then
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count <= count - 1;
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else
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if bitcount=0 then
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if wr='1' then -- START BIT
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shiftreg <= din;
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busy <= '1';
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txd <= '0';
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bitcount <= bitcount + 1;
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count <= unsigned(divisor);
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else
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busy <= '0';
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end if;
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elsif bitcount=9 then -- STOP BIT
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txd <= '1';
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bitcount <= 0;
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count <= unsigned(divisor);
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else -- DATA BIT
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shiftreg(6 downto 0) <= shiftreg(7 downto 1);
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txd <= shiftreg(0);
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bitcount <= bitcount + 1;
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count <= unsigned(divisor);
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end if;
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end if;
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end if;
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end if;
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end process;
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end rtl;
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