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Line 304... |
Interlaken Alliance,
|
Interlaken Alliance,
|
\textit{"Interlaken Interoperability Recommendations"}
|
\textit{"Interlaken Interoperability Recommendations"}
|
[On-line] Available:
|
[On-line] Available:
|
\url{http://www.interlakenalliance.com/interlaken-interoperability-recommendations-v1.10.pdf} [Apr. 03, 2018]
|
\url{http://www.interlakenalliance.com/interlaken-interoperability-recommendations-v1.10.pdf} [Apr. 03, 2018]
|
|
|
%Traditional CERN Protocols
|
|
\bibitem{S-Link}
|
|
Erik van der Bij,
|
|
\textit{"S-Link Overview"}
|
|
[On-line] Available:
|
|
\url{http://hsi.web.cern.ch/HSI/s-link/introduc/overview.htm} [Feb. 08, 2018]
|
|
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\bibitem{GBT_Frame}
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CERN,
|
|
\textit{"GBT ASIC presentation"}
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|
[On-line] Available:
|
|
\url{https://indico.cern.ch/event/49682/contributions/1175873/attachments/961783/1365381/2009_09_25_Implementing_the_GBT_data_transmission_protocol_in_FPGAs.pdf} [Feb. 08, 2018]
|
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%Hardware part
|
%Hardware part
|
\bibitem{Virtex-7}
|
|
Xilinx.
|
|
\textit{"7 Series FPGAs Data Sheet: Overview"}
|
|
[On-line] Available:
|
|
\url{https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf} [Feb. 19, 2018]
|
|
|
|
\bibitem{VC707}
|
\bibitem{VC707}
|
Xilinx.
|
Xilinx.
|
\textit{"VC707 Evaluation Board for the Virtex-7 FPGA - User Guide"}
|
\textit{"VC707 Evaluation Board for the Virtex-7 FPGA - User Guide"}
|
[On-line] Available:
|
[On-line] Available:
|
\url{https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf} [Feb. 19, 2018]
|
\url{https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf} [Feb. 19, 2018]
|
| Line 337... |
Line 317... |
Xilinx.
|
Xilinx.
|
\textit{"7 Series FPGAs GTX/GTH Transceivers - User Guide"}
|
\textit{"7 Series FPGAs GTX/GTH Transceivers - User Guide"}
|
[On-line] Available:
|
[On-line] Available:
|
\url{https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf} [Feb. 19, 2018]
|
\url{https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf} [Feb. 19, 2018]
|
|
|
\bibitem{CRC32}
|
\bibitem{VC707_Schematic}
|
Mathlab.
|
Xilinx.
|
\textit{"CRC-N Generator"}
|
\textit{"VC707 EVALUATION PLATFORM HW-V7-VC707 (XC7VX485T-FF1761)"}
|
[On-line] Available:
|
[On-Line] Available:
|
\url{https://nl.mathworks.com/help/comm/ref/crcngenerator.html} [Feb. 21, 2018]
|
\url{https://www.xilinx.com/support/documentation/boards_and_kits/vc707_Schematic_xtp135_rev1_0.pdf} [Feb. 19, 2018]
|
|
|
\bibitem{CRCpaper}
|
%Traditional CERN Protocols
|
Evgeni Stavinov.
|
\bibitem{S-Link}
|
\textit{"A Practical Parallel CRC Generation Method"}
|
Erik van der Bij,
|
|
\textit{"S-Link Overview"}
|
[On-line] Available:
|
[On-line] Available:
|
\url{http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf} [Feb. 22, 2018]
|
\url{http://hsi.web.cern.ch/HSI/s-link/introduc/overview.htm} [Feb. 08, 2018]
|
|
|
\bibitem{CRCgen}
|
\bibitem{GBT}
|
Evgeni Stavinov.
|
S. Baron, J.P. Cachemiche, F. Marin, P. Moreira, C. Soos,
|
\textit{"CRC Generator"}
|
\textit{"Implementing the GBT data transmission protocol in FPGAs"}
|
[On-line] Available:
|
[On-line] Available:
|
\url{http://outputlogic.com/?page_id=321} [Feb. 22, 2018]
|
\url{https://cds.cern.ch/record/1236361/files/p631.pdf} [July. 09, 2018]
|
|
|
\bibitem{Scramblergen}
|
\bibitem{GBT_LP}
|
Evgeni Stavinov.
|
A. Marchioro, P. Moreira,
|
\textit{"Scrambler Generator"}
|
\textit{"Low Power GBT"}
|
[On-line] Available:
|
[On-line] Available:
|
\url{http://outputlogic.com/?page_id=205} [Feb. 23, 2018]
|
\url{https://indico.cern.ch/event/153564/contributions/1397870/attachments/161703/228199/Marchioro_LP_GBT__FNAL_Nov_2011.pptx} [July. 09, 2018]
|
|
|
\bibitem{VC707_Schematic}
|
\bibitem{FELIX}
|
Xilinx.
|
J. Anderson, K. Bauer, A. Borga, H. Boterenbrood, H. Chen, K. Chen,G. Drake, M.Dönszelmann, D. Francis, D. Guest, B. Gorini, M. Joos, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, W. Panduro Vazquez, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, D. Whiteson, W. Wu and J. Zhang,
|
\textit{"VC707 EVALUATION PLATFORM HW-V7-VC707 (XC7VX485T-FF1761)"}
|
\textit{"FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework"}
|
[On-Line] Available:
|
[On-line] Available:
|
\url{https://www.xilinx.com/support/documentation/boards_and_kits/vc707_Schematic_xtp135_rev1_0.pdf} [Feb. 19, 2018]
|
\url{https://cds.cern.ch/record/2229597/files/ATL-DAQ-PROC-2016-022.pdf} [July. 09, 2018]
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\end{thebibliography}
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\end{thebibliography}
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\newpage
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\newpage
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No newline at end of file
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No newline at end of file
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