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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [deframing_burst_tb.vhd] - Diff between revs 6 and 9

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Rev 6 Rev 9
Line 6... Line 6...
 
 
architecture tb_deburster of testbench_deburster is
architecture tb_deburster of testbench_deburster is
 
 
    signal Clk          : std_logic;                     -- Clock input
    signal Clk          : std_logic;                     -- Clock input
        signal Reset            : std_logic;                                     -- Reset decoder
        signal Reset            : std_logic;                                     -- Reset decoder
 
 
        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
        signal Deburst_En   : std_logic;                     -- Enables the decoder
        signal Data_Out     : std_logic_vector(68 downto 0); -- Decoded 64-bit output
        signal Data_Out     : std_logic_vector(65 downto 0); -- Decoded 64-bit output
 
 
 
    signal Data_Control_In  : std_logic;                     -- Indicates whether the word is data or control
    signal Data_Control_In  : std_logic;                     -- Indicates whether the word is data or control
    signal Data_Control_Out : std_logic;                    --    Indicates whether the word is data or control
 
 
 
    signal CRC24_Error      : std_logic;
 
 
 
    signal Data_Valid_In    : std_logic;
    signal Data_Valid_In    : std_logic;
    signal Data_Valid_Out   : std_logic;
    signal Data_Valid_Out   : std_logic;
    signal FIFO_Full        : std_logic;
 
    signal FIFO_Data        : std_logic_vector(4 downto 0);
    signal CRC24_Error  : std_logic;
    signal FIFO_Write       : std_logic;
    signal Flowcontrol  : std_logic;
 
 
    constant CLK_PERIOD : time := 10 ns;
    constant CLK_PERIOD : time := 10 ns;
 
 
begin
begin
  uut : entity work.Burst_Deframer
  uut : entity work.Burst_Deframer

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