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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [deframing_meta_tb.vhd] - Diff between revs 6 and 9

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library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
entity testbench_deframer is
entity testbench_deframing_meta is
end entity testbench_deframer;
end entity testbench_deframing_meta;
 
 
architecture tb_deframer of testbench_deframer is
architecture tb_deframing_meta of testbench_deframing_meta is
 
 
    signal Clk          : std_logic;                     -- Clock input
    signal clk          : std_logic;                      -- Clock input
        signal Reset            : std_logic;                                     -- Reset decoder
        signal Reset            : std_logic;                                     -- Reset decoder
 
 
        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
        signal Data_In      : std_logic_vector(63 downto 0); -- Data input
        signal Deframer_En   : std_logic;                     -- Enables the decoder
 
        signal Data_Out     : std_logic_vector(63 downto 0); -- Decoded 64-bit output
        signal Data_Out     : std_logic_vector(63 downto 0); -- Decoded 64-bit output
 
 
 
        signal CRC32_Error   : std_logic;                     -- Enables the decoder
 
 
    signal Data_Control_In  : std_logic;                     -- Indicates whether the word is data or control
    signal Data_Control_In  : std_logic;                     -- Indicates whether the word is data or control
    signal Data_Control_Out : std_logic;                    --    Indicates whether the word is data or control
    signal Data_Control_Out : std_logic;                    --    Indicates whether the word is data or control
 
 
 
    signal Data_Valid_In    : std_logic;
    signal Data_Valid_Out   : std_logic;
    signal Data_Valid_Out   : std_logic;
 
 
    constant CLK_PERIOD : time := 10 ns;
    constant CLK_PERIOD : time := 10 ns;
 
 
begin
begin
  uut : entity work.Meta_Deframer
  uut : entity work.Meta_Deframer
  port map (
  port map (
    clk => clk,
    clk => clk,
    reset => reset,
    reset => reset,
    Deframer_En => Deframer_En,
 
 
        CRC32_Error => CRC32_Error,
 
 
    Data_in => Data_in,
    Data_in => Data_in,
    Data_out => Data_out,
    Data_out => Data_out,
 
 
    Data_control_in => Data_control_in,
    Data_control_in => Data_control_in,
    Data_control_out => Data_control_out,
    Data_control_out => Data_control_out,
 
 
 
        Data_valid_in => Data_valid_in,
    Data_valid_out => Data_valid_out
    Data_valid_out => Data_valid_out
  );
  );
 
 
   Clk_process :process
   Clk_process :process
     begin
     begin
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        data_in <= X"1f5e5d5c5b5a5958";
        data_in <= X"1f5e5d5c5b5a5958";
        wait for CLK_PERIOD;
        wait for CLK_PERIOD;
        wait;
        wait;
    end process;
    end process;
 
 
end architecture tb_deframer;
end architecture tb_deframing_meta;
 
 
 
 
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