| Line 4... |
Line 4... |
entity testbench_interlaken_receiver is
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entity testbench_interlaken_receiver is
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end entity testbench_interlaken_receiver;
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end entity testbench_interlaken_receiver;
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architecture tb_interlaken_receiver of testbench_interlaken_receiver is
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architecture tb_interlaken_receiver of testbench_interlaken_receiver is
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signal write_clk : std_logic;
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signal fifo_read_clk : std_logic;
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signal clk : std_logic;
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signal clk : std_logic;
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signal reset : std_logic;
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signal reset : std_logic;
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signal RX_Data_In : std_logic_vector(66 downto 0);
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signal RX_Data_In : std_logic_vector(66 downto 0);
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signal RX_Data_Out : std_logic_vector (63 downto 0); -- later 66 downto 0
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signal RX_Data_Out : std_logic_vector (63 downto 0); -- Data ready to transmit
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signal RX_Valid_Out : std_logic;
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signal RX_Enable : std_logic; -- Enable the TX
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signal RX_SOP : std_logic; -- Start of Packet
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signal RX_SOP : std_logic; -- Start of Packet
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signal RX_ValidBytes : std_logic_vector(2 downto 0); -- Valid bytes packet contains
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signal RX_EOP_Valid : std_logic_vector(2 downto 0); -- Valid bytes packet contains
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signal RX_EOP : std_logic; -- End of Packet
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signal RX_EOP : std_logic; -- End of Packet
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signal RX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
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signal RX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
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signal RX_prog_full : std_logic_vector(15 downto 0); -- Indication FIFO of this channel is full
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signal RX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
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signal RX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
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signal RX_Datavalid : std_logic;
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signal CRC24_Error : std_logic;
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signal CRC32_Error : std_logic;
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signal Decoder_lock : std_logic;
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signal Descrambler_lock : std_logic;
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signal Data_Descrambler : std_logic_vector(63 downto 0);
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signal Data_Decoder : std_logic_vector(63 downto 0);
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signal RX_FIFO_Full : std_logic;
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signal RX_FIFO_Read : std_logic;
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signal RX_Link_Up : std_logic;
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signal RX_Link_Up : std_logic;
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signal Bitslip : std_logic;
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : entity work.interlaken_receiver
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uut : entity work.interlaken_receiver
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| Line 55... |
Line 70... |
simulation : process
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simulation : process
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begin
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begin
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wait for 1 ps;
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wait for 1 ps;
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RX_Data_In <= (others=>'0');
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RX_Data_In <= (others=>'0');
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reset <= '1';
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reset <= '1';
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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--FIFO_meta <= '1';
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reset <= '0';
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reset <= '0';
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reset <= '0';
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reset <= '0';
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RX_Data_in <= "101" & X"1f5e5d5c5b5a5958";
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RX_Data_in <= "101" & X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
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RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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| Line 90... |
Line 97... |
RX_Data_In <= "101" & X"70000FFF000000F0";
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RX_Data_In <= "101" & X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD*2;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD;
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RX_Data_In <= "110" & X"8050505050050505";
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RX_Data_In <= "110" & X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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RX_Data_In <= "101" & X"9486576758050505";
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RX_Data_In <= "101" & X"9486576758050505";
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| Line 169... |
Line 173... |
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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wait for CLK_PERIOD*20;
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wait for CLK_PERIOD*20;
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD*10;
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wait for CLK_PERIOD*10;
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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| Line 188... |
Line 191... |
wait for CLK_PERIOD*6;
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wait for CLK_PERIOD*6;
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RX_Data_In <= "001" & X"8050505050050505";
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RX_Data_In <= "001" & X"8050505050050505";
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wait for CLK_PERIOD*9;
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wait for CLK_PERIOD*9;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "110" & X"8050505050050505";
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RX_Data_In <= "110" & X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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| Line 219... |
Line 221... |
wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"70000FFF000000F0";
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RX_Data_In <= "001" & X"70000FFF000000F0";
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wait for CLK_PERIOD*23;
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wait for CLK_PERIOD*23;
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RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--4 -> lock
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RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--4 -> lock
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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| Line 271... |
Line 271... |
RX_Data_In <= "001" & X"9486576758050505";
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RX_Data_In <= "001" & X"9486576758050505";
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wait for CLK_PERIOD*19;
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wait for CLK_PERIOD*19;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"8050505050050505";
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RX_Data_In <= "001" & X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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RX_Data_In <= "001" & X"9486576758050505";
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RX_Data_In <= "001" & X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"60b35d5dc4a582a7";
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RX_Data_In <= "001" & X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD*12;
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wait for CLK_PERIOD*12;
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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| Line 296... |
Line 293... |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"3f5e5d5c5b5a5958";
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RX_Data_In <= "001" & X"3f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"4f21a2a3a4a5a6a7";
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RX_Data_In <= "001" & X"4f21a2a3a4a5a6a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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| Line 320... |
Line 314... |
wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"70000FFF000000F0";
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RX_Data_In <= "001" & X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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wait for CLK_PERIOD*2;
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"8050505050050505";
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RX_Data_In <= "001" & X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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| Line 339... |
Line 332... |
wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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RX_Data_In <= "001" & X"9486576758050505";
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RX_Data_In <= "001" & X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"60b35d5dc4a582a7";
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RX_Data_In <= "001" & X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"60b35d5dc4a582a7";
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RX_Data_In <= "101" & X"60b35d5dc4a582a7";
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wait for CLK_PERIOD*60;
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wait for CLK_PERIOD*60;
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RX_Data_In <= "110" & X"8050505050050505";
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RX_Data_In <= "110" & X"8050505050050505";
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wait for CLK_PERIOD*3;
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wait for CLK_PERIOD*3;
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RX_Data_In <= "101" & X"9486576758050505";
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RX_Data_In <= "101" & X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"60b35d5dc4a582a7";
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RX_Data_In <= "101" & X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD*12;
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wait for CLK_PERIOD*12;
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RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
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RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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| Line 371... |
Line 360... |
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RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
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RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
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wait for CLK_PERIOD*18;
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wait for CLK_PERIOD*18;
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RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
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RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait;
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--FIFO_meta <= '0';
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wait for CLK_PERIOD*4;
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--FIFO_meta <= '1';
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wait;
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wait;
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end process;
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end process;
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end architecture tb_interlaken_receiver;
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end architecture tb_interlaken_receiver;
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