| Line 11... |
Line 11... |
signal reset : std_logic;
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signal reset : std_logic;
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signal TX_Data_In : std_logic_vector(63 downto 0);
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signal TX_Data_In : std_logic_vector(63 downto 0);
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signal TX_Data_Out : std_logic_vector (66 downto 0); -- later 66 downto 0
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signal TX_Data_Out : std_logic_vector (66 downto 0); -- later 66 downto 0
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signal TX_Enable : std_logic; -- Enable the TX
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signal TX_SOP : std_logic; -- Start of Packet
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signal TX_SOP : std_logic; -- Start of Packet
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signal TX_ValidBytes : std_logic_vector(2 downto 0); -- Valid bytes packet contains
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signal TX_EOP_Valid : std_logic_vector(2 downto 0); -- Valid bytes packet contains
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signal TX_EOP : std_logic; -- End of Packet
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signal TX_EOP : std_logic; -- End of Packet
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signal TX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
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signal TX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
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signal TX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
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signal TX_Gearboxready : std_logic;
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signal TX_Startseq : std_logic;
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signal TX_Link_Up : std_logic;
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signal TX_FlowControl : std_logic_vector(15 downto 0);
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signal RX_prog_full : std_logic_vector(15 downto 0);
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signal TX_Valid_Out : std_logic;
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signal FIFO_Write_Data : std_logic;
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signal TX_Control_Out : std_logic;
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signal FIFO_prog_full : std_logic;
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signal FIFO_Full : std_logic;
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signal Link_up : std_logic;
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signal TX_valid_out : std_logic;
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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begin
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begin
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uut : entity work.interlaken_transmitter
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uut : entity work.interlaken_transmitter
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port map (
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port map (
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write_clk => write_clk,
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write_clk => write_clk,
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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TX_Data_In => TX_Data_In,
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TX_Data_In => TX_Data_In,
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TX_Data_Out => TX_Data_Out,
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TX_Data_Out => TX_Data_Out,
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TX_Enable => TX_Enable,
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TX_SOP => TX_SOP,
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TX_SOP => TX_SOP,
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TX_ValidBytes => TX_ValidBytes,
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TX_EOP_Valid=> TX_ValidBytes,
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TX_EOP => TX_EOP,
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TX_EOP => TX_EOP,
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TX_FlowControl => TX_FlowControl,
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TX_Channel => TX_Channel,
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TX_Channel => TX_Channel,
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TX_Gearboxready => TX_Gearboxready,
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TX_Startseq => TX_Startseq,
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TX_FlowControl => TX_FlowControl,
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RX_prog_full => RX_prog_full,
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FIFO_Write_Data => FIFO_Write_Data,
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FIFO_prog_full => FIFO_prog_full,
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FIFO_Full => FIFO_Full,
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TX_Link_Up => TX_Link_Up,
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Link_up => Link_up,
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TX_Valid_Out => TX_Valid_Out,
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TX_valid_out => TX_valid_out
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TX_Control_Out => TX_Control_Out
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);
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);
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Clk_process :process
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Clk_process :process
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begin
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begin
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write_clk <= '1';
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write_clk <= '1';
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| Line 118... |
Line 131... |
TX_SOP <= '0';
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TX_SOP <= '0';
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TX_EOP <= '1';
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TX_EOP <= '1';
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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TX_EOP <= '0';
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TX_EOP <= '0';
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--TX_SOP <= '0';
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TX_data_in <= X"8050505050050505";
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TX_data_in <= X"8050505050050505";
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--wait for CLK_PERIOD*3;
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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TX_data_in <= X"9486576758050505";
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TX_data_in <= X"9486576758050505";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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TX_EOP <= '1';
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TX_EOP <= '1';
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TX_data_in <= X"60b35d5dc4a582a7";
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TX_data_in <= X"60b35d5dc4a582a7";
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| Line 169... |
Line 181... |
TX_Data_in <= X"4f5e5d5c5b5a5958";
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TX_Data_in <= X"4f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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wait for CLK_PERIOD;
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TX_SOP <= '0';
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TX_SOP <= '0';
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TX_EOP <= '1';
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TX_EOP <= '1';
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wait for CLK_PERIOD;
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--FIFO_meta <= '0';
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wait for CLK_PERIOD*4;
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--FIFO_meta <= '1';
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wait;
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wait;
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end process;
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end process;
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end architecture tb_interlaken_transmitter;
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end architecture tb_interlaken_transmitter;
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