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/*
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* Automatically generated C config: don't edit
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*/
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#define AUTOCONF_INCLUDED
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/*
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* Synthesis
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*/
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#undef CONFIG_SYN_GENERIC
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#undef CONFIG_SYN_ATC35
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#undef CONFIG_SYN_ATC25
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#undef CONFIG_SYN_ATC18
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#undef CONFIG_SYN_FS90
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#undef CONFIG_SYN_UMC018
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#undef CONFIG_SYN_TSMC025
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#undef CONFIG_SYN_PROASIC
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#undef CONFIG_SYN_AXCEL
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#undef CONFIG_SYN_VIRTEX
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#define CONFIG_SYN_VIRTEX2 1
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#undef CONFIG_SYN_INFER_RAM
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#undef CONFIG_SYN_INFER_REGF
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#undef CONFIG_SYN_INFER_ROM
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#undef CONFIG_SYN_INFER_PCI_PADS
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#undef CONFIG_SYN_INFER_MULT
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#undef CONFIG_SYN_RFTYPE
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#undef CONFIG_SYN_TRACE_DPRAM
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/*
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* ------------------ Xilinx Clock generation ------------------
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*/
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/*
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* Clock generation
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*/
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#undef CONFIG_CLK_VIRTEX
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#undef CONFIG_CLK_VIRTEX2
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#undef CONFIG_PCI_DLL
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#undef CONFIG_PCI_SYSCLK
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/*
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* Target Architecture
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*/
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#define CONFIG_TARGET_ARM 1
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#undef CONFIG_TARGET_SPARC
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#undef CONFIG_TARGET_M68K
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/*
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* Target ARM
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*/
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/*
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* Integer unit
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*/
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/*
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* Cache system
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*/
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/*
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* Instruction cache
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*/
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#define CONFIG_ICACHE_ASSO1 1
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#undef CONFIG_ICACHE_ASSO2
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#undef CONFIG_ICACHE_ASSO3
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#undef CONFIG_ICACHE_ASSO4
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#define CONFIG_ICACHE_SZ1 1
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#undef CONFIG_ICACHE_SZ2
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#undef CONFIG_ICACHE_SZ4
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#undef CONFIG_ICACHE_SZ8
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#undef CONFIG_ICACHE_SZ16
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#undef CONFIG_ICACHE_SZ32
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#undef CONFIG_ICACHE_SZ64
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#define CONFIG_ICACHE_LZ4 1
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#undef CONFIG_ICACHE_LZ8
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#undef CONFIG_GENICACHE_LOCK
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/*
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* Data cache
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*/
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#undef CONFIG_DCACHE_WRITEBACK
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#define CONFIG_DCACHE_WRITETHROUGH 1
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#define CONFIG_DCACHE_ASSO1 1
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#undef CONFIG_DCACHE_ASSO2
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#undef CONFIG_DCACHE_ASSO3
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#undef CONFIG_DCACHE_ASSO4
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#define CONFIG_DCACHE_SZ1 1
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#undef CONFIG_DCACHE_SZ2
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#undef CONFIG_DCACHE_SZ4
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#undef CONFIG_DCACHE_SZ8
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#undef CONFIG_DCACHE_SZ16
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#undef CONFIG_DCACHE_SZ32
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#undef CONFIG_DCACHE_SZ64
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#define CONFIG_DCACHE_LZ4 1
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#undef CONFIG_DCACHE_LZ8
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#undef CONFIG_GENDCACHE_LOCK
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#undef CONFIG_DCACHE_WB_SZ1
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#define CONFIG_DCACHE_WB_SZ2 1
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#undef CONFIG_DCACHE_WB_SZ4
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#undef CONFIG_DCACHE_WB_SZ8
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#undef CONFIG_DCACHE_WB_SZ16
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/*
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* Amba bus
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*/
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#define CONFIG_AHB_DEFMST (0)
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#undef CONFIG_AHB_SPLIT
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#undef CONFIG_PERI_AHBSTAT
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/*
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* Peripherals
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*/
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/*
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* Memory
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*/
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/*
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* Memory controller
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*/
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#define CONFIG_MCTRL_8BIT 1
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#define CONFIG_MCTRL_16BIT 1
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#define CONFIG_PERI_WPROT 1
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#define CONFIG_MCTRL_WFB 1
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#define CONFIG_MCTRL_5CS 1
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#define CONFIG_MCTRL_SDRAM 1
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#define CONFIG_MCTRL_SDRAM_INVCLK 1
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/*
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* On chip ram
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*/
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#undef CONFIG_AHBRAM_ENABLE
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/*
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* Serial
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*/
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/*
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* VHDL Debugging
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*/
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#undef CONFIG_DEBUG_UART
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/*
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* ARM debugging
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*/
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