?rev1line? |
?rev2line? |
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# vsim tbench
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# Loading c:/Modeltech_5.4e/win32/../std.standard
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# Loading c:/Modeltech_5.4e/win32/../ieee.std_logic_1164(body)
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# Loading work.tbench_comp
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# Loading c:/Modeltech_5.4e/win32/../ieee.std_logic_arith(body)
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# Loading work.leon_target
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# Loading work.leon_device
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# Loading c:/Modeltech_5.4e/win32/../std.textio(body)
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# Loading work.leon_config
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# Loading work.debug(body)
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# Loading work.mmuconfig
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# Loading work.sparcv8
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# Loading work.leon_iface
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# Loading work.core_config
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# Loading work.corelib
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# Loading work.amba
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# Loading work.peri_serial_comp
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# Loading work.peri_io_comp
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# Loading work.peri_mem_comp
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# Loading work.core_comp
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# Loading work.tbenchmem_comp
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# Loading work.tbench
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# Loading work.tbench_config(behav)
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# Loading work.memdef(body)
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# Loading work.config
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# Loading work.tech_map
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# Loading work.ctrl_comp
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# Loading c:/Modeltech_5.4e/win32/../ieee.std_logic_unsigned(body)
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# Loading work.macro(body)
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# Loading work.mti_pkg(body)
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# Loading work.tbench_gen(behav)
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# Loading work.bus_comp
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# Loading work.cache_config
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# Loading work.int(body)
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# Loading work.gencmem_lib(body)
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# Loading work.gendc_lib(body)
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# Loading work.genic_lib(body)
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# Loading work.genwb_lib
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# Loading work.cache_comp
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# Loading work.armpmodel(body)
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# Loading work.armshiefter(body)
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# Loading work.armdecode(body)
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# Loading work.armpctrl(body)
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# Loading work.arm_comp
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# Loading work.tech_generic
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# Loading work.tech_virtex
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# Loading work.tech_virtex2
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# Loading work.tech_atc18
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# Loading work.tech_atc25
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# Loading work.tech_atc35
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# Loading work.tech_fs90
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# Loading work.tech_umc18
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# Loading work.tech_tsmc25
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# Loading work.core(rtl)
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# Loading work.peri_mem_config
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# Loading work.ctrl_config
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# Loading work.log(body)
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# Loading work.soc_gen(rtl)
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# Loading work.ahbarb(rtl)
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# Loading work.apbmst(rtl)
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# Loading work.armcoproc(body)
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# Loading work.armcp_comp
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# Loading work.arm_proc(rtl)
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# Loading work.armdebug(body)
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# Loading work.armcmd(body)
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# Loading work.armldst(body)
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# Loading work.armcmd_comp
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# Loading work.armctrl(body)
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# Loading work.armsctrl(body)
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# Loading work.armiu(rtl)
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# Loading work.armiu_imstg(rtl)
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# Loading work.armiu_festg(rtl)
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# Loading work.armiu_destg(rtl)
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# Loading work.armiu_drstg(rtl)
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# Loading work.armcmd_al(rtl)
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# Loading work.armcmd_sr(rtl)
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# Loading work.armcmd_ld(rtl)
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# Loading work.armcmd_st(rtl)
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# Loading work.armcmd_lm(rtl)
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# Loading work.armcmd_sm(rtl)
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# Loading work.armcmd_sw(rtl)
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# Loading work.armcmd_cr(rtl)
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# Loading work.armcmd_cl(rtl)
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# Loading work.armcmd_cs(rtl)
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# Loading work.armcmd_bl(rtl)
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# Loading work.tech_proasic
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# Loading work.tech_axcel
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# Loading work.armiu_rrstg(rtl)
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# Loading work.tech_atc18_syn
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# Loading work.tech_atc25_syn
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# Loading work.tech_atc35_syn
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# Loading work.tech_fs90_syn
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# Loading work.tech_umc18_syn
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# Loading work.tech_tsmc25_syn
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# Loading work.regfile_iu(rtl)
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# Loading work.virtex2_complib
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# Loading work.virtex2_regfile(behav)
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# Loading work.virtex2_dpram(behav)
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# Loading work.ramb16_s36_s36(behav)
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# Loading work.ram16_sx_sx(behav)
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# Loading work.armiu_rsstg(rtl)
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# Loading work.armiu_exstg(rtl)
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# Loading work.armiu_dmstg(rtl)
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# Loading work.armiu_mestg(rtl)
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# Loading work.armiu_wrstg(rtl)
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# Loading work.armcp_sctrl(rtl)
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# Loading work.setrepl_lib(body)
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# Loading work.arith_cnt_comp
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# Loading work.armcache(rtl)
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# Loading work.genic(rtl)
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# Loading work.gendc(rtl)
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# Loading work.arith_cnt8(rtl)
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# Loading work.setrepl(rtl)
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# Loading work.genwb(rtl)
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# Loading work.genwbfifo(rtl)
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# Loading work.gencmem(rtl)
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# Loading work.virtex_complib
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# Loading work.syncram(behav)
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# Loading work.virtex2_syncram(behav)
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# Loading work.ramb16_s36(behav)
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# Loading work.generic_syncram(behavioral)
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# Loading work.ahbmst_mp(rtl)
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# Loading work.mctrl(rtl)
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# Loading work.sdmctrl(rtl)
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# Loading work.timers(rtl)
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# Loading work.irqctrl(rtl)
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# Loading work.clkgen(rtl)
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# Loading work.generic_clkgen(rtl)
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# Loading work.smpad(rtl)
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# Loading work.gensmpad(rtl)
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# Loading work.rstgen(rtl)
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# Loading work.outpad(rtl)
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# Loading work.genoutpad(rtl)
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# Loading work.iopad(rtl)
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# Loading work.geniopad(rtl)
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# Loading work.inpad(rtl)
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# Loading work.geninpad(rtl)
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# Loading work.smiopad(rtl)
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# Loading work.iram(behavioral)
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# Loading work.mt48lc16m16a2(behave)
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view wave
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# .wave
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do vsim/sctrl
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write format wave -window .wave C:/cygwin/home/eiselekd/vhdl_0.8/vsim/sctrl
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write format wave -window .wave C:/cygwin/home/eiselekd/vhdl_0.8/vsim/sctrl
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view atm
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# Bad window name: atm
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view vsim/arm
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# Bad window name: vsim/arm
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do vsim/arm
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run 10000
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# Core generic testbench
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# 32 kbyte 32-bit rom, 0-ws
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# 2x128 kbyte 32-bit ram, 2x64 Mbyte SDRAM
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#
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