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-- 10/24/2005
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-- General Purpose Register Bank
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library ieee;
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use ieee.std_logic_1164.all;
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entity registers is port(
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d: in std_logic_vector(15 downto 0);
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clk: in std_logic;
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addr_a: in std_logic_vector(2 downto 0);
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addr_b: in std_logic_vector(2 downto 0);
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wr_en: in std_logic;
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a_o: out std_logic_vector(15 downto 0);
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b_o: out std_logic_vector(15 downto 0)
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);
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end registers;
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architecture regs_arch of registers is
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component reg port(
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d: in std_logic_vector(15 downto 0);
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clk: in std_logic;
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wr_en: in std_logic;
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q: out std_logic_vector(15 downto 0)
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);
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end component;
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component reg_dec port(
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addr: in std_logic_vector(2 downto 0);
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en0: out std_logic;
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en1: out std_logic;
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en2: out std_logic;
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en3: out std_logic;
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en4: out std_logic;
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en5: out std_logic;
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en6: out std_logic;
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en7: out std_logic
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);
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end component;
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component mux_8_1 port(
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a: in std_logic_vector(15 downto 0);
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b: in std_logic_vector(15 downto 0);
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c: in std_logic_vector(15 downto 0);
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d: in std_logic_vector(15 downto 0);
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e: in std_logic_vector(15 downto 0);
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f: in std_logic_vector(15 downto 0);
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g: in std_logic_vector(15 downto 0);
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h: in std_logic_vector(15 downto 0);
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sel: in std_logic_vector(2 downto 0);
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o: out std_logic_vector(15 downto 0)
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);
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end component;
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signal w0, w1, w2, w3, w4, w5, w6, w7: std_logic;
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signal q0, q1, q2, q3, q4, q5, q6, q7: std_logic_vector(15 downto 0);
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signal wr_clk: std_logic;
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begin
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wr_clk <= wr_en and clk;
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decode: reg_dec
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port map(addr_a, w0, w1, w2, w3, w4, w5, w6, w7);
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r0: reg
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port map(d, wr_clk, w0, q0);
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r1: reg
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port map(d, wr_clk, w1, q1);
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r2: reg
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port map(d, wr_clk, w2, q2);
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r3: reg
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port map(d, wr_clk, w3, q3);
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r4: reg
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port map(d, wr_clk, w4, q4);
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r5: reg
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port map(d, wr_clk, w5, q5);
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r6: reg
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port map(d, wr_clk, w6, q6);
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r7: reg
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port map(d, wr_clk, w7, q7);
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out_mux_a: mux_8_1
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port map(q0, q1, q2, q3, q4, q5, q6, q7, addr_a, a_o);
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out_mux_b: mux_8_1
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port map(q0, q1, q2, q3, q4, q5, q6, q7, addr_b, b_o);
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end regs_arch;
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No newline at end of file
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