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[/] [cpu16/] [trunk/] [cpu16.v] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 15... Line 15...
 *
 *
 * You should have received a copy of the GNU General Public License
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */
 */
 
 
 
// comment this line out to use LE's (warning: size goes up dramatically to around 800LE's)
 
`define USE_RAM_FOR_REGFILE
 
 
 
 
module cpu16 (
module cpu16 (
        clk,
        clk,
        reset_n,
        reset_n,
        clk_en,
        clk_en,
        address,
        address,
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                        ra_dst = 3'd6;  // hard linked register
                        ra_dst = 3'd6;  // hard linked register
                else
                else
                        ra_dst = ir_dst;
                        ra_dst = ir_dst;
 
 
        // register file        
        // register file        
 
        `ifdef USE_RAM_FOR_REGFILE
        wire [15:0] qa, qb;
        wire [15:0] qa, qb;
        regfile8x16 i_regfile (
        regfile8x16 i_regfile (
                .clock(clk),
                .clock(clk),
                .data(reg_data),
                .data(reg_data),
                .rdaddress_a(ir_dst),
                .rdaddress_a(ir_dst),
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                .wraddress(ra_dst),
                .wraddress(ra_dst),
                .wren(reg_write&clk_en),
                .wren(reg_write&clk_en),
                .qa(qa),
                .qa(qa),
                .qb(qb)
                .qb(qb)
                );
                );
 
        `else
 
                reg [15:0] regs[7:0];
 
                always @(posedge clk)
 
                        if (reg_write&clk_en)
 
                                regs[ir_dst] <= reg_data;
 
                wire [15:0] qa = regs[ir_dst];
 
                wire [15:0] qb = regs[ir_src];
 
        `endif
 
 
        // flags
        // flags
        reg i, next_i;
        reg i, next_i;
        reg n, next_n;
        reg n, next_n;
        reg v, next_v;
        reg v, next_v;

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