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https://opencores.org/ocsvn/cpu16/cpu16/trunk
[/] [cpu16/] [trunk/] [cpu16.v] - Diff between revs 2 and 3
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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*/
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// comment this line out to use LE's (warning: size goes up dramatically to around 800LE's)
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`define USE_RAM_FOR_REGFILE
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module cpu16 (
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module cpu16 (
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clk,
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clk,
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reset_n,
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reset_n,
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clk_en,
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clk_en,
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address,
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address,
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Line 420... |
ra_dst = 3'd6; // hard linked register
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ra_dst = 3'd6; // hard linked register
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else
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else
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ra_dst = ir_dst;
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ra_dst = ir_dst;
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// register file
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// register file
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`ifdef USE_RAM_FOR_REGFILE
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wire [15:0] qa, qb;
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wire [15:0] qa, qb;
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regfile8x16 i_regfile (
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regfile8x16 i_regfile (
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.clock(clk),
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.clock(clk),
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.data(reg_data),
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.data(reg_data),
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.rdaddress_a(ir_dst),
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.rdaddress_a(ir_dst),
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Line 432... |
.wraddress(ra_dst),
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.wraddress(ra_dst),
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.wren(reg_write&clk_en),
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.wren(reg_write&clk_en),
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.qa(qa),
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.qa(qa),
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.qb(qb)
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.qb(qb)
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);
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);
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`else
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reg [15:0] regs[7:0];
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always @(posedge clk)
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if (reg_write&clk_en)
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regs[ir_dst] <= reg_data;
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wire [15:0] qa = regs[ir_dst];
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wire [15:0] qb = regs[ir_src];
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`endif
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// flags
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// flags
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reg i, next_i;
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reg i, next_i;
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reg n, next_n;
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reg n, next_n;
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reg v, next_v;
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reg v, next_v;
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