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-- VHDL Entity R6502_TC.fsm_nmi.symbol
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-- VHDL Entity R6502_TC.FSM_NMI.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- by - eda.UNKNOWN (TEST)
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-- at - 19:07:10 08.04.2008
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-- at - 21:30:26 04.01.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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entity fsm_nmi is
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ENTITY FSM_NMI IS
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port(
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PORT(
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clk_clk_i : in std_logic;
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clk_clk_i : IN std_logic;
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nmi_n_i : in std_logic;
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fetch_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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nmi_n_i : IN std_logic;
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nmi_o : out std_logic
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rst_rst_n_i : IN std_logic;
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nmi_o : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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end fsm_nmi ;
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END FSM_NMI ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- scantara2003@yahoo.de
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-- scantara2003@yahoo.de
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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--
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-- <<-- more -->>
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-- Title: FSM for NMI
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-- Title: FSM for NMI
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-- Path: R6502_TC/fsm_nmi/fsm
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-- Path: R6502_TC/FSM_NMI/fsm
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-- Edited: by eda on 08 Apr 2008
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-- Edited: by eda on 03 Jan 2009
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--
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--
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-- VHDL Architecture R6502_TC.fsm_nmi.fsm
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-- VHDL Architecture R6502_TC.FSM_NMI.fsm
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- by - eda.UNKNOWN (TEST)
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-- at - 19:07:11 08.04.2008
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-- at - 21:30:26 04.01.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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architecture fsm of fsm_nmi is
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ARCHITECTURE fsm OF FSM_NMI IS
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type state_type is (
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TYPE STATE_TYPE IS (
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idle,
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idle,
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idle1,
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idle1,
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idle2,
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idle2,
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IMP
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IMP
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);
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);
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-- State vector declaration
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-- State vector declaration
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attribute state_vector : string;
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ATTRIBUTE state_vector : string;
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attribute state_vector of fsm : architecture is "current_state";
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ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";
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-- Declare current and next state signals
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-- Declare current and next state signals
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signal current_state : state_type;
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SIGNAL current_state : STATE_TYPE;
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signal next_state : state_type;
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SIGNAL next_state : STATE_TYPE;
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-- Declare any pre-registered internal signals
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-- Declare any pre-registered internal signals
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signal nmi_o_cld : std_logic ;
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SIGNAL nmi_o_cld : std_logic ;
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begin
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BEGIN
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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clocked_proc : process (
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clocked_proc : PROCESS (
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clk_clk_i,
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clk_clk_i,
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rst_rst_n_i
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rst_rst_n_i
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)
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)
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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begin
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BEGIN
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if (rst_rst_n_i = '0') then
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IF (rst_rst_n_i = '0') THEN
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current_state <= idle;
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current_state <= idle;
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-- Default Reset Values
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-- Default Reset Values
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nmi_o_cld <= '0';
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nmi_o_cld <= '0';
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elsif (clk_clk_i'event and clk_clk_i = '1') then
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ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
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current_state <= next_state;
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current_state <= next_state;
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-- Default Assignment To Internals
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-- Default Assignment To Internals
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nmi_o_cld <= '0';
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nmi_o_cld <= '0';
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-- Combined Actions
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-- Combined Actions
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case current_state is
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CASE current_state IS
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when IMP =>
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WHEN IMP =>
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nmi_o_cld <= '1';
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nmi_o_cld <= '1';
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when others =>
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WHEN OTHERS =>
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null;
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NULL;
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end case;
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END CASE;
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end if;
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END IF;
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end process clocked_proc;
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END PROCESS clocked_proc;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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nextstate_proc : process (
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nextstate_proc : PROCESS (
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current_state,
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current_state,
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fetch_i,
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nmi_n_i
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nmi_n_i
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)
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)
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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begin
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BEGIN
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case current_state is
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CASE current_state IS
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when idle =>
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WHEN idle =>
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if (nmi_n_i = '1') then
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IF (nmi_n_i = '1') THEN
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next_state <= idle1;
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next_state <= idle1;
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else
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ELSE
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next_state <= idle;
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next_state <= idle;
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end if;
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END IF;
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when idle1 =>
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WHEN idle1 =>
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if (nmi_n_i = '0') then
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IF (nmi_n_i = '0') THEN
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next_state <= idle2;
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next_state <= idle2;
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else
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ELSE
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next_state <= idle1;
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next_state <= idle1;
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end if;
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END IF;
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when idle2 =>
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WHEN idle2 =>
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if (nmi_n_i = '0') then
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IF (nmi_n_i = '0') THEN
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next_state <= IMP;
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next_state <= IMP;
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else
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ELSE
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next_state <= idle;
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next_state <= idle;
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end if;
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END IF;
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when IMP =>
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WHEN IMP =>
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IF (fetch_i = '1') THEN
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next_state <= idle;
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next_state <= idle;
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when others =>
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ELSE
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next_state <= IMP;
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END IF;
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WHEN OTHERS =>
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next_state <= idle;
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next_state <= idle;
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end case;
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END CASE;
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end process nextstate_proc;
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END PROCESS nextstate_proc;
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-- Concurrent Statements
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-- Concurrent Statements
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-- Clocked output assignments
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-- Clocked output assignments
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nmi_o <= nmi_o_cld;
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nmi_o <= nmi_o_cld;
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end fsm;
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END fsm;
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No newline at end of file
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