URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [TO_DO_list.txt] - Diff between revs 18 and 24

Rev 18	Rev 24
Line 1...	Line 1...
	`(March 15th 2010)`
	`- (DONE) Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by`
	`simulation with RTI and in a real environment by customer.`
	`- (DONE) Removed directory ./verilog_TRIAL from source.`
	`- (DONE) Updated HTML`

`(February 25th 2009)`	`(February 25th 2009)`
`- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)`	`- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)`
`- (DONE) RENAME all states of "FSM Execution Unit" for better reading`	`- (DONE) RENAME all states of "FSM Execution Unit" for better reading`
`- (90%) Finish working for Specification of cpu6502_tc`	`- (90%) Finish working for Specification of cpu6502_tc`