| Line 1... |
Line 1... |
-- VHDL Entity R6502_TC.Core.symbol
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-- VHDL Entity R6502_TC.Core.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:49:03 17.04.2008
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-- at - 22:53:21 04.01.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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| Line 44... |
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- CVS Revisins History
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-- CVS Revisins History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Title: Core of 6502
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-- <<-- more -->>
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-- Title: Core
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-- Path: R6502_TC/Core/struct
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-- Path: R6502_TC/Core/struct
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-- Edited: by eda on 17 Apr 2008
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-- Edited: by eda on 04 Jan 2009
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--
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--
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-- VHDL Architecture R6502_TC.Core.struct
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-- VHDL Architecture R6502_TC.Core.struct
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--
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--
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-- Created:
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-- Created:
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:49:03 17.04.2008
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-- at - 22:53:22 04.01.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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| Line 68... |
Line 69... |
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_nxt_sp_o_i : std_logic_vector(15 downto 0);
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signal adr_o_i : std_logic_vector(15 downto 0);
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signal adr_o_i : std_logic_vector(15 downto 0);
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signal adr_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_sp_o_i : std_logic_vector(15 downto 0);
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signal adr_sp_o_i : std_logic_vector(15 downto 0);
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signal ch_a_o_i : std_logic_vector(7 downto 0);
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signal ch_a_o_i : std_logic_vector(7 downto 0);
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signal ch_b_o_i : std_logic_vector(7 downto 0);
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signal ch_b_o_i : std_logic_vector(7 downto 0);
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signal cout_pc_o_i : std_logic;
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signal d_alu_n_o_i : std_logic;
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signal d_alu_o_i : std_logic_vector(7 downto 0);
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signal d_alu_o_i : std_logic_vector(7 downto 0);
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signal d_alu_or_o_i : std_logic;
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signal d_regs_in_o_i : std_logic_vector(7 downto 0);
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signal d_regs_in_o_i : std_logic_vector(7 downto 0);
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signal d_regs_out_o_i : std_logic_vector(7 downto 0);
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signal d_regs_out_o_i : std_logic_vector(7 downto 0);
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signal fetch_o_i : std_logic;
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signal fetch_o_i : std_logic;
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signal ld_o_i : std_logic_vector(1 downto 0);
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signal ld_o_i : std_logic_vector(1 downto 0);
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signal ld_pc_o_i : std_logic;
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signal ld_pc_o_i : std_logic;
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| Line 88... |
Line 89... |
signal nmi_o_i : std_logic;
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signal nmi_o_i : std_logic;
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signal offset_o_i : std_logic_vector(15 downto 0);
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signal offset_o_i : std_logic_vector(15 downto 0);
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signal q_a_o_i : std_logic_vector(7 downto 0);
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signal q_a_o_i : std_logic_vector(7 downto 0);
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signal q_x_o_i : std_logic_vector(7 downto 0);
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signal q_x_o_i : std_logic_vector(7 downto 0);
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signal q_y_o_i : std_logic_vector(7 downto 0);
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signal q_y_o_i : std_logic_vector(7 downto 0);
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signal reg_0flag_core_o_i : std_logic;
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signal reg_0flag_o_i : std_logic;
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signal reg_0flag_o_i : std_logic;
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signal reg_1flag_o_i : std_logic;
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signal reg_1flag_o_i : std_logic;
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signal reg_3flag_core_o_i : std_logic;
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signal reg_6flag_o_i : std_logic;
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signal reg_7flag_core_o_i : std_logic;
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signal reg_7flag_o_i : std_logic;
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signal reg_7flag_o_i : std_logic;
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signal rst_rst_int_o_i : std_logic;
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signal sel_alu_as_o_i : std_logic;
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signal sel_alu_out_o_i : std_logic_vector(2 downto 0);
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signal sel_pc_as_o_i : std_logic;
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signal sel_pc_as_o_i : std_logic;
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signal sel_pc_in_o_i : std_logic_vector(1 downto 0);
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signal sel_pc_in_o_i : std_logic;
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signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
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signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
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signal sel_rb_in_o_i : std_logic_vector(2 downto 0);
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signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
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signal sel_rb_out_o_i : std_logic_vector(2 downto 0);
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signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
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signal sel_reg_o_i : std_logic_vector(1 downto 0);
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signal sel_reg_o_i : std_logic_vector(1 downto 0);
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signal sel_sp_as_o_i : std_logic;
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signal sel_sp_as_o_i : std_logic;
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signal sel_sp_in_o_i : std_logic_vector(1 downto 0);
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signal sel_sp_in_o_i : std_logic;
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signal sel_sp_val_o_i : std_logic_vector(1 downto 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
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signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
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signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
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signal mw_U_11sum : unsigned(8 downto 0);
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-- Component Declarations
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-- Component Declarations
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component ALU
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component FSM_Execution_Unit
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port (
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ch_a_i : in std_logic_vector (7 downto 0);
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ch_b_i : in std_logic_vector (7 downto 0);
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reg_0flag_core_i : in std_logic ;
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reg_3flag_core_i : in std_logic ;
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reg_7flag_core_i : in std_logic ;
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sel_alu_as_i : in std_logic ;
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sel_alu_out_i : in std_logic_vector (2 downto 0);
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d_alu_o : out std_logic_vector (7 downto 0);
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reg_0flag_o : out std_logic ;
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reg_1flag_o : out std_logic ;
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reg_6flag_o : out std_logic ;
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reg_7flag_o : out std_logic
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);
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end component;
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component RegBank_AXY
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port (
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clk_clk_i : in std_logic ;
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d_regs_in_i : in std_logic_vector (7 downto 0);
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load_regs_i : in std_logic ;
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rst_rst_i : in std_logic ;
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sel_rb_in_i : in std_logic_vector (2 downto 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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d_regs_out_o : out std_logic_vector (7 downto 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_x_o : out std_logic_vector (7 downto 0);
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q_y_o : out std_logic_vector (7 downto 0)
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);
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end component;
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component Reg_PC
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port (
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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ld_i : in std_logic_vector (1 downto 0);
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ld_pc_i : in std_logic ;
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offset_i : in std_logic_vector (15 downto 0);
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rst_rst_i : in std_logic ;
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sel_pc_as_i : in std_logic ;
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sel_pc_in_i : in std_logic ;
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sel_pc_val_i : in std_logic_vector (1 downto 0);
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adr_nxt_pc_o : out std_logic_vector (15 downto 0);
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adr_pc_o : out std_logic_vector (15 downto 0);
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cout_pc_o : out std_logic
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);
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end component;
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component Reg_SP
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port (
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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ld_i : in std_logic_vector (1 downto 0);
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ld_sp_i : in std_logic ;
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rst_rst_i : in std_logic ;
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sel_sp_as_i : in std_logic ;
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sel_sp_in_i : in std_logic ;
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sel_sp_val_i : in std_logic ;
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adr_nxt_sp_o : out std_logic_vector (15 downto 0);
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adr_sp_o : out std_logic_vector (15 downto 0)
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);
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end component;
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component fsm_core_V2_0
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port (
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port (
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adr_nxt_pc_i : in std_logic_vector (15 downto 0);
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adr_nxt_pc_i : in std_logic_vector (15 downto 0);
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adr_nxt_sp_i : in std_logic_vector (15 downto 0);
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adr_pc_i : in std_logic_vector (15 downto 0);
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adr_pc_i : in std_logic_vector (15 downto 0);
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adr_sp_i : in std_logic_vector (15 downto 0);
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adr_sp_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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clk_clk_i : in std_logic ;
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cout_pc_i : in std_logic ;
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d_alu_i : in std_logic_vector ( 7 downto 0 );
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d_alu_i : in std_logic_vector ( 7 downto 0 );
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d_i : in std_logic_vector ( 7 downto 0 );
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d_i : in std_logic_vector ( 7 downto 0 );
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d_regs_out_i : in std_logic_vector ( 7 downto 0 );
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d_regs_out_i : in std_logic_vector ( 7 downto 0 );
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irq_n_i : in std_logic ;
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irq_n_i : in std_logic ;
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nmi_i : in std_logic ;
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nmi_i : in std_logic ;
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| Line 190... |
Line 125... |
q_x_i : in std_logic_vector ( 7 downto 0 );
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q_x_i : in std_logic_vector ( 7 downto 0 );
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q_y_i : in std_logic_vector ( 7 downto 0 );
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q_y_i : in std_logic_vector ( 7 downto 0 );
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rdy_i : in std_logic ;
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rdy_i : in std_logic ;
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reg_0flag_i : in std_logic ;
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reg_0flag_i : in std_logic ;
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reg_1flag_i : in std_logic ;
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reg_1flag_i : in std_logic ;
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reg_6flag_i : in std_logic ;
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reg_7flag_i : in std_logic ;
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reg_7flag_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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so_n_i : in std_logic ;
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so_n_i : in std_logic ;
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a_o : out std_logic_vector (15 downto 0);
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a_o : out std_logic_vector (15 downto 0);
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adr_o : out std_logic_vector (15 downto 0);
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adr_o : out std_logic_vector (15 downto 0);
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| Line 207... |
Line 141... |
ld_pc_o : out std_logic ;
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ld_pc_o : out std_logic ;
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ld_sp_o : out std_logic ;
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ld_sp_o : out std_logic ;
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load_regs_o : out std_logic ;
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load_regs_o : out std_logic ;
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offset_o : out std_logic_vector ( 15 downto 0 );
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offset_o : out std_logic_vector ( 15 downto 0 );
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rd_o : out std_logic ;
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rd_o : out std_logic ;
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reg_0flag_o : out std_logic ;
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sel_pc_as_o : out std_logic ;
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reg_1flag_o : out std_logic ;
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sel_pc_in_o : out std_logic ;
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reg_3flag_o : out std_logic ;
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sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
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reg_7flag_o : out std_logic ;
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sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
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sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
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sel_reg_o : out std_logic_vector ( 1 downto 0 );
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sel_sp_as_o : out std_logic ;
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sel_sp_in_o : out std_logic ;
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sync_o : out std_logic ;
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sync_o : out std_logic ;
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wr_n_o : out std_logic ;
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wr_n_o : out std_logic ;
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wr_o : out std_logic ;
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wr_o : out std_logic
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sel_alu_as_o_i : inout std_logic ;
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sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 );
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sel_pc_as_o_i : inout std_logic ;
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sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 );
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sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 );
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sel_reg_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_sp_as_o_i : inout std_logic ;
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sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 )
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);
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);
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end component;
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end component;
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component fsm_nmi
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component FSM_NMI
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port (
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port (
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clk_clk_i : in std_logic ;
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clk_clk_i : in std_logic ;
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fetch_i : in std_logic ;
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fetch_i : in std_logic ;
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nmi_n_i : in std_logic ;
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nmi_n_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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nmi_o : out std_logic
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nmi_o : out std_logic
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);
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);
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end component;
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end component;
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component RegBank_AXY
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port (
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clk_clk_i : in std_logic ;
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d_regs_in_i : in std_logic_vector (7 downto 0);
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load_regs_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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sel_rb_in_i : in std_logic_vector (1 downto 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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d_regs_out_o : out std_logic_vector (7 downto 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_x_o : out std_logic_vector (7 downto 0);
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q_y_o : out std_logic_vector (7 downto 0)
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);
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end component;
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component Reg_PC
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port (
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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ld_i : in std_logic_vector (1 downto 0);
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ld_pc_i : in std_logic ;
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offset_i : in std_logic_vector (15 downto 0);
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rst_rst_n_i : in std_logic ;
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sel_pc_as_i : in std_logic ;
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sel_pc_in_i : in std_logic ;
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sel_pc_val_i : in std_logic_vector (1 downto 0);
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adr_nxt_pc_o : out std_logic_vector (15 downto 0);
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adr_pc_o : out std_logic_vector (15 downto 0)
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);
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end component;
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component Reg_SP
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port (
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adr_low_i : in std_logic_vector (7 downto 0);
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clk_clk_i : in std_logic ;
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ld_low_i : in std_logic ;
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ld_sp_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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sel_sp_as_i : in std_logic ;
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sel_sp_in_i : in std_logic ;
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adr_sp_o : out std_logic_vector (15 downto 0)
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);
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end component;
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|
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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for all : ALU use entity R6502_TC.ALU;
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for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
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for all : FSM_NMI use entity R6502_TC.FSM_NMI;
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for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
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for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
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for all : Reg_PC use entity R6502_TC.Reg_PC;
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for all : Reg_PC use entity R6502_TC.Reg_PC;
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for all : Reg_SP use entity R6502_TC.Reg_SP;
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for all : Reg_SP use entity R6502_TC.Reg_SP;
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for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;
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for all : fsm_nmi use entity R6502_TC.fsm_nmi;
|
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-- pragma synthesis_on
|
-- pragma synthesis_on
|
|
|
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|
begin
|
begin
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|
|
-- ModuleWare code(v1.9) for instance 'U_5' of 'inv'
|
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
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rst_rst_int_o_i <= not(rst_rst_n_i);
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mw_U_11temp_din0 <= '0' & ch_a_o_i;
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mw_U_11temp_din1 <= '0' & ch_b_o_i;
|
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u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
|
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variable temp_carry : std_logic;
|
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begin
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temp_carry := '0';
|
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mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
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end process u_11combo_proc;
|
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d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
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reg_0flag_o_i <= mw_U_11sum(8) ;
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-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
|
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reg_1flag_o_i <= not(d_alu_or_o_i);
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-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
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reg_7flag_o_i <= not(d_alu_n_o_i);
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-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
|
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d_alu_n_o_i <= not(d_alu_o_i(7));
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|
|
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-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
|
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d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
|
|
|
-- Instance port mappings.
|
-- Instance port mappings.
|
U_3 : ALU
|
U_4 : FSM_Execution_Unit
|
port map (
|
|
ch_a_i => ch_a_o_i,
|
|
ch_b_i => ch_b_o_i,
|
|
reg_0flag_core_i => reg_0flag_core_o_i,
|
|
reg_3flag_core_i => reg_3flag_core_o_i,
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|
reg_7flag_core_i => reg_7flag_core_o_i,
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|
sel_alu_as_i => sel_alu_as_o_i,
|
|
sel_alu_out_i => sel_alu_out_o_i,
|
|
d_alu_o => d_alu_o_i,
|
|
reg_0flag_o => reg_0flag_o_i,
|
|
reg_1flag_o => reg_1flag_o_i,
|
|
reg_6flag_o => reg_6flag_o_i,
|
|
reg_7flag_o => reg_7flag_o_i
|
|
);
|
|
U_2 : RegBank_AXY
|
|
port map (
|
|
clk_clk_i => clk_clk_i,
|
|
d_regs_in_i => d_regs_in_o_i,
|
|
load_regs_i => load_regs_o_i,
|
|
rst_rst_i => rst_rst_int_o_i,
|
|
sel_rb_in_i => sel_rb_in_o_i,
|
|
sel_rb_out_i => sel_rb_out_o_i(1 DOWNTO 0),
|
|
sel_reg_i => sel_reg_o_i,
|
|
d_regs_out_o => d_regs_out_o_i,
|
|
q_a_o => q_a_o_i,
|
|
q_x_o => q_x_o_i,
|
|
q_y_o => q_y_o_i
|
|
);
|
|
U_0 : Reg_PC
|
|
port map (
|
|
adr_i => adr_o_i,
|
|
clk_clk_i => clk_clk_i,
|
|
ld_i => ld_o_i,
|
|
ld_pc_i => ld_pc_o_i,
|
|
offset_i => offset_o_i,
|
|
rst_rst_i => rst_rst_int_o_i,
|
|
sel_pc_as_i => sel_pc_as_o_i,
|
|
sel_pc_in_i => sel_pc_in_o_i(0),
|
|
sel_pc_val_i => sel_pc_val_o_i,
|
|
adr_nxt_pc_o => adr_nxt_pc_o_i,
|
|
adr_pc_o => adr_pc_o_i,
|
|
cout_pc_o => cout_pc_o_i
|
|
);
|
|
U_1 : Reg_SP
|
|
port map (
|
|
adr_i => adr_o_i,
|
|
clk_clk_i => clk_clk_i,
|
|
ld_i => ld_o_i,
|
|
ld_sp_i => ld_sp_o_i,
|
|
rst_rst_i => rst_rst_int_o_i,
|
|
sel_sp_as_i => sel_sp_as_o_i,
|
|
sel_sp_in_i => sel_sp_in_o_i(0),
|
|
sel_sp_val_i => sel_sp_val_o_i(0),
|
|
adr_nxt_sp_o => adr_nxt_sp_o_i,
|
|
adr_sp_o => adr_sp_o_i
|
|
);
|
|
U_4 : fsm_core_V2_0
|
|
port map (
|
port map (
|
adr_nxt_pc_i => adr_nxt_pc_o_i,
|
adr_nxt_pc_i => adr_nxt_pc_o_i,
|
adr_nxt_sp_i => adr_nxt_sp_o_i,
|
|
adr_pc_i => adr_pc_o_i,
|
adr_pc_i => adr_pc_o_i,
|
adr_sp_i => adr_sp_o_i,
|
adr_sp_i => adr_sp_o_i,
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
cout_pc_i => cout_pc_o_i,
|
|
d_alu_i => d_alu_o_i,
|
d_alu_i => d_alu_o_i,
|
d_i => d_i,
|
d_i => d_i,
|
d_regs_out_i => d_regs_out_o_i,
|
d_regs_out_i => d_regs_out_o_i,
|
irq_n_i => irq_n_i,
|
irq_n_i => irq_n_i,
|
nmi_i => nmi_o_i,
|
nmi_i => nmi_o_i,
|
| Line 330... |
Line 260... |
q_x_i => q_x_o_i,
|
q_x_i => q_x_o_i,
|
q_y_i => q_y_o_i,
|
q_y_i => q_y_o_i,
|
rdy_i => rdy_i,
|
rdy_i => rdy_i,
|
reg_0flag_i => reg_0flag_o_i,
|
reg_0flag_i => reg_0flag_o_i,
|
reg_1flag_i => reg_1flag_o_i,
|
reg_1flag_i => reg_1flag_o_i,
|
reg_6flag_i => reg_6flag_o_i,
|
|
reg_7flag_i => reg_7flag_o_i,
|
reg_7flag_i => reg_7flag_o_i,
|
rst_rst_n_i => rst_rst_n_i,
|
rst_rst_n_i => rst_rst_n_i,
|
so_n_i => so_n_i,
|
so_n_i => so_n_i,
|
a_o => a_o,
|
a_o => a_o,
|
adr_o => adr_o_i,
|
adr_o => adr_o_i,
|
| Line 347... |
Line 276... |
ld_pc_o => ld_pc_o_i,
|
ld_pc_o => ld_pc_o_i,
|
ld_sp_o => ld_sp_o_i,
|
ld_sp_o => ld_sp_o_i,
|
load_regs_o => load_regs_o_i,
|
load_regs_o => load_regs_o_i,
|
offset_o => offset_o_i,
|
offset_o => offset_o_i,
|
rd_o => rd_o,
|
rd_o => rd_o,
|
reg_0flag_o => reg_0flag_core_o_i,
|
sel_pc_as_o => sel_pc_as_o_i,
|
reg_1flag_o => open,
|
sel_pc_in_o => sel_pc_in_o_i,
|
reg_3flag_o => reg_3flag_core_o_i,
|
sel_pc_val_o => sel_pc_val_o_i,
|
reg_7flag_o => reg_7flag_core_o_i,
|
sel_rb_in_o => sel_rb_in_o_i,
|
|
sel_rb_out_o => sel_rb_out_o_i,
|
|
sel_reg_o => sel_reg_o_i,
|
|
sel_sp_as_o => sel_sp_as_o_i,
|
|
sel_sp_in_o => sel_sp_in_o_i,
|
sync_o => sync_o,
|
sync_o => sync_o,
|
wr_n_o => wr_n_o,
|
wr_n_o => wr_n_o,
|
wr_o => wr_o,
|
wr_o => wr_o
|
sel_alu_as_o_i => sel_alu_as_o_i,
|
|
sel_alu_out_o_i => sel_alu_out_o_i,
|
|
sel_pc_as_o_i => sel_pc_as_o_i,
|
|
sel_pc_in_o_i => sel_pc_in_o_i,
|
|
sel_pc_val_o_i => sel_pc_val_o_i,
|
|
sel_rb_in_o_i => sel_rb_in_o_i,
|
|
sel_rb_out_o_i => sel_rb_out_o_i,
|
|
sel_reg_o_i => sel_reg_o_i,
|
|
sel_sp_as_o_i => sel_sp_as_o_i,
|
|
sel_sp_in_o_i => sel_sp_in_o_i,
|
|
sel_sp_val_o_i => sel_sp_val_o_i
|
|
);
|
);
|
U_6 : fsm_nmi
|
U_6 : FSM_NMI
|
port map (
|
port map (
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
fetch_i => fetch_o_i,
|
fetch_i => fetch_o_i,
|
nmi_n_i => nmi_n_i,
|
nmi_n_i => nmi_n_i,
|
rst_rst_n_i => rst_rst_n_i,
|
rst_rst_n_i => rst_rst_n_i,
|
nmi_o => nmi_o_i
|
nmi_o => nmi_o_i
|
);
|
);
|
|
U_2 : RegBank_AXY
|
|
port map (
|
|
clk_clk_i => clk_clk_i,
|
|
d_regs_in_i => d_regs_in_o_i,
|
|
load_regs_i => load_regs_o_i,
|
|
rst_rst_n_i => rst_rst_n_i,
|
|
sel_rb_in_i => sel_rb_in_o_i,
|
|
sel_rb_out_i => sel_rb_out_o_i,
|
|
sel_reg_i => sel_reg_o_i,
|
|
d_regs_out_o => d_regs_out_o_i,
|
|
q_a_o => q_a_o_i,
|
|
q_x_o => q_x_o_i,
|
|
q_y_o => q_y_o_i
|
|
);
|
|
U_0 : Reg_PC
|
|
port map (
|
|
adr_i => adr_o_i,
|
|
clk_clk_i => clk_clk_i,
|
|
ld_i => ld_o_i,
|
|
ld_pc_i => ld_pc_o_i,
|
|
offset_i => offset_o_i,
|
|
rst_rst_n_i => rst_rst_n_i,
|
|
sel_pc_as_i => sel_pc_as_o_i,
|
|
sel_pc_in_i => sel_pc_in_o_i,
|
|
sel_pc_val_i => sel_pc_val_o_i,
|
|
adr_nxt_pc_o => adr_nxt_pc_o_i,
|
|
adr_pc_o => adr_pc_o_i
|
|
);
|
|
U_1 : Reg_SP
|
|
port map (
|
|
adr_low_i => adr_o_i(7 DOWNTO 0),
|
|
clk_clk_i => clk_clk_i,
|
|
ld_low_i => ld_o_i(0),
|
|
ld_sp_i => ld_sp_o_i,
|
|
rst_rst_n_i => rst_rst_n_i,
|
|
sel_sp_as_i => sel_sp_as_o_i,
|
|
sel_sp_in_i => sel_sp_in_o_i,
|
|
adr_sp_o => adr_sp_o_i
|
|
);
|
|
|
end struct;
|
end struct;
|
|
|
No newline at end of file
|
No newline at end of file
|
