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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [core.vhd] - Diff between revs 3 and 5

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Line 1... Line 1... 
-- VHDL Entity R6502_TC.Core.symbol
 
-- VHDL Entity R6502_TC.Core.symbol
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          at - 19:07:10 08.04.2008
 
--          at - 19:49:03 17.04.2008
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
Line 13... Line 13... 
entity Core is
 
entity Core is
 
   port(
 
   port(
 
      clk_clk_i   : in     std_logic;
 
      clk_clk_i   : in     std_logic;
 
      d_i         : in     std_logic_vector (7 downto 0);
 
      d_i         : in     std_logic_vector (7 downto 0);
 
      irq_n_i     : in     std_logic;
 
      irq_n_i     : in     std_logic;
 
      nmi_i       : in     std_logic;
 
      nmi_n_i     : in     std_logic;
 
      rdy_i       : in     std_logic;
 
      rdy_i       : in     std_logic;
 
      rst_rst_n_i : in     std_logic;
 
      rst_rst_n_i : in     std_logic;
 
      so_n_i      : in     std_logic;
 
      so_n_i      : in     std_logic;
 
      a_o         : out    std_logic_vector (15 downto 0);
 
      a_o         : out    std_logic_vector (15 downto 0);
 
      d_o         : out    std_logic_vector (7 downto 0);
 
      d_o         : out    std_logic_vector (7 downto 0);
Line 44... Line 44... 
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.                                                  
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.                                                  
--                                                                                                                                                                                          
--                                                                                                                                                                                          
-- CVS Revisins History                                                                                                                                                                     
-- CVS Revisins History                                                                                                                                                                     
--                                                                                                                                                                                          
--                                                                                                                                                                                          
-- $Log: not supported by cvs2svn $                                                                                                                                                                                    
-- $Log: not supported by cvs2svn $                                                                                                                                                                                    
--                                                                                                                                                                                          
 
 
-- Title:  Core of 6502  
-- Title:  Core of 6502  
-- Path:  R6502_TC/Core/struct  
-- Path:  R6502_TC/Core/struct  
-- Edited:  by eda on 08 Apr 2008  
-- Edited:  by eda on 17 Apr 2008  
--
 
--
 
-- VHDL Architecture R6502_TC.Core.struct
 
-- VHDL Architecture R6502_TC.Core.struct
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          at - 19:07:10 08.04.2008
 
--          at - 19:49:03 17.04.2008
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
Line 79... Line 78... 
   signal ch_b_o_i           : std_logic_vector(7 downto 0);
 
   signal ch_b_o_i           : std_logic_vector(7 downto 0);
 
   signal cout_pc_o_i        : std_logic;
 
   signal cout_pc_o_i        : std_logic;
 
   signal d_alu_o_i          : std_logic_vector(7 downto 0);
 
   signal d_alu_o_i          : std_logic_vector(7 downto 0);
 
   signal d_regs_in_o_i      : std_logic_vector(7 downto 0);
 
   signal d_regs_in_o_i      : std_logic_vector(7 downto 0);
 
   signal d_regs_out_o_i     : std_logic_vector(7 downto 0);
 
   signal d_regs_out_o_i     : std_logic_vector(7 downto 0);
 
 
 
   signal fetch_o_i          : std_logic;
 
   signal ld_o_i             : std_logic_vector(1 downto 0);
 
   signal ld_o_i             : std_logic_vector(1 downto 0);
 
   signal ld_pc_o_i          : std_logic;
 
   signal ld_pc_o_i          : std_logic;
 
   signal ld_sp_o_i          : std_logic;
 
   signal ld_sp_o_i          : std_logic;
 
   signal load_regs_o_i      : std_logic;
 
   signal load_regs_o_i      : std_logic;
 
 
 
   signal nmi_o_i            : std_logic;
 
   signal offset_o_i         : std_logic_vector(15 downto 0);
 
   signal offset_o_i         : std_logic_vector(15 downto 0);
 
   signal q_a_o_i            : std_logic_vector(7 downto 0);
 
   signal q_a_o_i            : std_logic_vector(7 downto 0);
 
   signal q_x_o_i            : std_logic_vector(7 downto 0);
 
   signal q_x_o_i            : std_logic_vector(7 downto 0);
 
   signal q_y_o_i            : std_logic_vector(7 downto 0);
 
   signal q_y_o_i            : std_logic_vector(7 downto 0);
 
   signal reg_0flag_core_o_i : std_logic;
 
   signal reg_0flag_core_o_i : std_logic;
Line 199... Line 200... 
      adr_o           : out    std_logic_vector (15 downto 0);
 
      adr_o           : out    std_logic_vector (15 downto 0);
 
      ch_a_o          : out    std_logic_vector ( 7 downto 0 );
 
      ch_a_o          : out    std_logic_vector ( 7 downto 0 );
 
      ch_b_o          : out    std_logic_vector ( 7 downto 0 );
 
      ch_b_o          : out    std_logic_vector ( 7 downto 0 );
 
      d_o             : out    std_logic_vector ( 7 downto 0 );
 
      d_o             : out    std_logic_vector ( 7 downto 0 );
 
      d_regs_in_o     : out    std_logic_vector ( 7 downto 0 );
 
      d_regs_in_o     : out    std_logic_vector ( 7 downto 0 );
 
 
 
      fetch_o         : out    std_logic ;
 
      ld_o            : out    std_logic_vector ( 1 downto 0 );
 
      ld_o            : out    std_logic_vector ( 1 downto 0 );
 
      ld_pc_o         : out    std_logic ;
 
      ld_pc_o         : out    std_logic ;
 
      ld_sp_o         : out    std_logic ;
 
      ld_sp_o         : out    std_logic ;
 
      load_regs_o     : out    std_logic ;
 
      load_regs_o     : out    std_logic ;
 
      offset_o        : out    std_logic_vector ( 15 downto 0 );
 
      offset_o        : out    std_logic_vector ( 15 downto 0 );
Line 225... Line 227... 
      sel_sp_as_o_i   : inout  std_logic ;
 
      sel_sp_as_o_i   : inout  std_logic ;
 
      sel_sp_in_o_i   : inout  std_logic_vector ( 1 downto 0 );
 
      sel_sp_in_o_i   : inout  std_logic_vector ( 1 downto 0 );
 
      sel_sp_val_o_i  : inout  std_logic_vector ( 1 downto 0 )
 
      sel_sp_val_o_i  : inout  std_logic_vector ( 1 downto 0 )
 
   );
 
   );
 
   end component;
 
   end component;
 
 
 
   component fsm_nmi
 
 
 
   port (
 
 
 
      clk_clk_i   : in     std_logic ;
 
 
 
      fetch_i     : in     std_logic ;
 
 
 
      nmi_n_i     : in     std_logic ;
 
 
 
      rst_rst_n_i : in     std_logic ;
 
 
 
      nmi_o       : out    std_logic
 
 
 
   );
 
 
 
   end component;
 
 
 
 
 
   -- Optional embedded configurations
 
   -- Optional embedded configurations
 
   -- pragma synthesis_off
 
   -- pragma synthesis_off
 
   for all : ALU use entity R6502_TC.ALU;
 
   for all : ALU use entity R6502_TC.ALU;
 
   for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
 
   for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
 
   for all : Reg_PC use entity R6502_TC.Reg_PC;
 
   for all : Reg_PC use entity R6502_TC.Reg_PC;
 
   for all : Reg_SP use entity R6502_TC.Reg_SP;
 
   for all : Reg_SP use entity R6502_TC.Reg_SP;
 
   for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;
 
   for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;
 
 
 
   for all : fsm_nmi use entity R6502_TC.fsm_nmi;
 
   -- pragma synthesis_on
 
   -- pragma synthesis_on
 
 
 
 
 
 
 
 
 
begin
 
begin
 
 
 
 
Line 311... Line 323... 
         cout_pc_i       => cout_pc_o_i,
 
         cout_pc_i       => cout_pc_o_i,
 
         d_alu_i         => d_alu_o_i,
 
         d_alu_i         => d_alu_o_i,
 
         d_i             => d_i,
 
         d_i             => d_i,
 
         d_regs_out_i    => d_regs_out_o_i,
 
         d_regs_out_i    => d_regs_out_o_i,
 
         irq_n_i         => irq_n_i,
 
         irq_n_i         => irq_n_i,
 
         nmi_i           => nmi_i,
 
         nmi_i           => nmi_o_i,
 
         q_a_i           => q_a_o_i,
 
         q_a_i           => q_a_o_i,
 
         q_x_i           => q_x_o_i,
 
         q_x_i           => q_x_o_i,
 
         q_y_i           => q_y_o_i,
 
         q_y_i           => q_y_o_i,
 
         rdy_i           => rdy_i,
 
         rdy_i           => rdy_i,
 
         reg_0flag_i     => reg_0flag_o_i,
 
         reg_0flag_i     => reg_0flag_o_i,
Line 328... Line 340... 
         adr_o           => adr_o_i,
 
         adr_o           => adr_o_i,
 
         ch_a_o          => ch_a_o_i,
 
         ch_a_o          => ch_a_o_i,
 
         ch_b_o          => ch_b_o_i,
 
         ch_b_o          => ch_b_o_i,
 
         d_o             => d_o,
 
         d_o             => d_o,
 
         d_regs_in_o     => d_regs_in_o_i,
 
         d_regs_in_o     => d_regs_in_o_i,
 
 
 
         fetch_o         => fetch_o_i,
 
         ld_o            => ld_o_i,
 
         ld_o            => ld_o_i,
 
         ld_pc_o         => ld_pc_o_i,
 
         ld_pc_o         => ld_pc_o_i,
 
         ld_sp_o         => ld_sp_o_i,
 
         ld_sp_o         => ld_sp_o_i,
 
         load_regs_o     => load_regs_o_i,
 
         load_regs_o     => load_regs_o_i,
 
         offset_o        => offset_o_i,
 
         offset_o        => offset_o_i,
Line 353... Line 366... 
         sel_reg_o_i     => sel_reg_o_i,
 
         sel_reg_o_i     => sel_reg_o_i,
 
         sel_sp_as_o_i   => sel_sp_as_o_i,
 
         sel_sp_as_o_i   => sel_sp_as_o_i,
 
         sel_sp_in_o_i   => sel_sp_in_o_i,
 
         sel_sp_in_o_i   => sel_sp_in_o_i,
 
         sel_sp_val_o_i  => sel_sp_val_o_i
 
         sel_sp_val_o_i  => sel_sp_val_o_i
 
      );
 
      );
 
 
 
   U_6 : fsm_nmi
 
 
 
      port map (
 
 
 
         clk_clk_i   => clk_clk_i,
 
 
 
         fetch_i     => fetch_o_i,
 
 
 
         nmi_n_i     => nmi_n_i,
 
 
 
         rst_rst_n_i => rst_rst_n_i,
 
 
 
         nmi_o       => nmi_o_i
 
 
 
      );
 
 
 
 
 
end struct;
 
end struct;
 
 
 
 
 
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