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-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
--
-- Created:
-- Created:
--          by - eda.UNKNOWN (TEST)
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 19:21:47 07.01.2009
--          at - 11:47:40 23.02.2009
--
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
--
LIBRARY ieee;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_arith.all;
 
 
ENTITY FSM_Execution_Unit IS
entity FSM_Execution_Unit is
   PORT(
   port(
      adr_nxt_pc_i : IN     std_logic_vector (15 DOWNTO 0);
      adr_nxt_pc_i : in     std_logic_vector (15 downto 0);
      adr_pc_i     : IN     std_logic_vector (15 DOWNTO 0);
      adr_pc_i     : in     std_logic_vector (15 downto 0);
      adr_sp_i     : IN     std_logic_vector (15 DOWNTO 0);
      adr_sp_i     : in     std_logic_vector (15 downto 0);
      clk_clk_i    : IN     std_logic;
      clk_clk_i    : in     std_logic;
      d_alu_i      : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_alu_i      : in     std_logic_vector ( 7 downto 0 );
      d_i          : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_i          : in     std_logic_vector ( 7 downto 0 );
      d_regs_out_i : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_regs_out_i : in     std_logic_vector ( 7 downto 0 );
      irq_n_i      : IN     std_logic;
      irq_n_i      : in     std_logic;
      nmi_i        : IN     std_logic;
      nmi_i        : in     std_logic;
      q_a_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_a_i        : in     std_logic_vector ( 7 downto 0 );
      q_x_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_x_i        : in     std_logic_vector ( 7 downto 0 );
      q_y_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_y_i        : in     std_logic_vector ( 7 downto 0 );
      rdy_i        : IN     std_logic;
      rdy_i        : in     std_logic;
      reg_0flag_i  : IN     std_logic;
      reg_0flag_i  : in     std_logic;
      reg_1flag_i  : IN     std_logic;
      reg_1flag_i  : in     std_logic;
      reg_7flag_i  : IN     std_logic;
      reg_7flag_i  : in     std_logic;
      rst_rst_n_i  : IN     std_logic;
      rst_rst_n_i  : in     std_logic;
      so_n_i       : IN     std_logic;
      so_n_i       : in     std_logic;
      a_o          : OUT    std_logic_vector (15 DOWNTO 0);
      a_o          : out    std_logic_vector (15 downto 0);
      adr_o        : OUT    std_logic_vector (15 DOWNTO 0);
      adr_o        : out    std_logic_vector (15 downto 0);
      ch_a_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
      ch_a_o       : out    std_logic_vector ( 7 downto 0 );
      ch_b_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
      ch_b_o       : out    std_logic_vector ( 7 downto 0 );
      d_o          : OUT    std_logic_vector ( 7 DOWNTO 0 );
      d_o          : out    std_logic_vector ( 7 downto 0 );
      d_regs_in_o  : OUT    std_logic_vector ( 7 DOWNTO 0 );
      d_regs_in_o  : out    std_logic_vector ( 7 downto 0 );
      fetch_o      : OUT    std_logic;
      fetch_o      : out    std_logic;
      ld_o         : OUT    std_logic_vector ( 1 DOWNTO 0 );
      ld_o         : out    std_logic_vector ( 1 downto 0 );
      ld_pc_o      : OUT    std_logic;
      ld_pc_o      : out    std_logic;
      ld_sp_o      : OUT    std_logic;
      ld_sp_o      : out    std_logic;
      load_regs_o  : OUT    std_logic;
      load_regs_o  : out    std_logic;
      offset_o     : OUT    std_logic_vector ( 15 DOWNTO 0 );
      offset_o     : out    std_logic_vector ( 15 downto 0 );
      rd_o         : OUT    std_logic;
      rd_o         : out    std_logic;
      sel_pc_in_o  : OUT    std_logic;
      sel_pc_in_o  : out    std_logic;
      sel_pc_val_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_pc_val_o : out    std_logic_vector ( 1 downto 0 );
      sel_rb_in_o  : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_rb_in_o  : out    std_logic_vector ( 1 downto 0 );
      sel_rb_out_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_rb_out_o : out    std_logic_vector ( 1 downto 0 );
      sel_reg_o    : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_reg_o    : out    std_logic_vector ( 1 downto 0 );
      sel_sp_as_o  : OUT    std_logic;
      sel_sp_as_o  : out    std_logic;
      sel_sp_in_o  : OUT    std_logic;
      sel_sp_in_o  : out    std_logic;
      sync_o       : OUT    std_logic;
      sync_o       : out    std_logic;
      wr_n_o       : OUT    std_logic;
      wr_o         : out    std_logic
      wr_o         : OUT    std_logic
 
   );
   );
 
 
-- Declarations
-- Declarations
 
 
END FSM_Execution_Unit ;
end FSM_Execution_Unit ;
 
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- Jens-D. Gutschmidt     Project:  R6502_TC  
 
 
-- scantara2003@yahoo.de                      
-- scantara2003@yahoo.de                      
 
 
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG                                                                                
 
 
--                                                                                                                                             
--                                                                                                                                             
 
 
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   
 
 
Line 93... Line 92...
 
 
-- Title:  FSM Execution Unit for all op codes  
-- Title:  FSM Execution Unit for all op codes  
 
 
-- Path:  R6502_TC/FSM_Execution_Unit/fsm  
-- Path:  R6502_TC/FSM_Execution_Unit/fsm  
 
 
-- Edited:  by eda on 07 Jan 2009  
-- Edited:  by eda on 23 Feb 2009  
 
 
--
--
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
--
-- Created:
-- Created:
--          by - eda.UNKNOWN (TEST)
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 19:21:50 07.01.2009
--          at - 11:47:41 23.02.2009
--
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
--
LIBRARY ieee;
library ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
use ieee.std_logic_arith.ALL;
 
 
ARCHITECTURE fsm OF FSM_Execution_Unit IS
architecture fsm of FSM_Execution_Unit is
 
 
   -- Architecture Declarations
   -- Architecture Declarations
   SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
   signal reg_F : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL reg_sel_pc_in : std_logic;
   signal reg_sel_pc_in : std_logic;
   SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
   signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
   SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
   signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
   SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
   signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
   SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
   signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
   SIGNAL reg_sel_sp_as : std_logic;
   signal reg_sel_sp_as : std_logic;
   SIGNAL reg_sel_sp_in : std_logic;
   signal reg_sel_sp_in : std_logic;
   SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
   signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
   signal sig_PC : std_logic_vector(15 DOWNTO 0);
   SIGNAL sig_RD : std_logic;
   signal sig_SYNC : std_logic;
   SIGNAL sig_RWn : std_logic;
   signal sig_WR : std_logic;
   SIGNAL sig_SYNC : std_logic;
   signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
   SIGNAL sig_WR : std_logic;
   signal zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
   SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
   signal zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
   SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
   signal zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
   SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
   signal zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
   SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
   signal zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
   SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
   signal zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
   SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
   signal zw_REG_NMI : std_logic;
   SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
   signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL zw_REG_NMI : std_logic;
   signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
   signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
   signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
   signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
   signal zw_so : std_logic;
   SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
 
   SIGNAL zw_so : std_logic;
 
 
 
   SUBTYPE STATE_TYPE IS
   subtype state_type is
      std_logic_vector(7 DOWNTO 0);
      std_logic_vector(7 downto 0);
 
 
   -- Hard encoding
   -- Hard encoding
   CONSTANT FETCH : STATE_TYPE := "00000000";
   constant FETCH : state_type := "00000000";
   CONSTANT s1 : STATE_TYPE := "00000001";
   constant G10_1 : state_type := "00000001";
   CONSTANT s2 : STATE_TYPE := "00000011";
   constant G10_2 : state_type := "00000010";
   CONSTANT s5 : STATE_TYPE := "00000010";
   constant G10_3 : state_type := "00000011";
   CONSTANT s3 : STATE_TYPE := "00000110";
   constant G10_4 : state_type := "00000100";
   CONSTANT s4 : STATE_TYPE := "00000111";
   constant G10_5 : state_type := "00000101";
   CONSTANT s12 : STATE_TYPE := "00000101";
   constant G10_6 : state_type := "00000110";
   CONSTANT s16 : STATE_TYPE := "00000100";
   constant G10_7 : state_type := "00000111";
   CONSTANT s17 : STATE_TYPE := "00001100";
   constant G10_e1 : state_type := "00001000";
   CONSTANT s24 : STATE_TYPE := "00001101";
   constant G10_e2 : state_type := "00001001";
   CONSTANT s25 : STATE_TYPE := "00001111";
   constant G10_e3 : state_type := "00001010";
   CONSTANT s271 : STATE_TYPE := "00001110";
   constant G11_1 : state_type := "00001011";
   CONSTANT s273 : STATE_TYPE := "00001010";
   constant G11_2 : state_type := "00001100";
   CONSTANT s304 : STATE_TYPE := "00001011";
   constant G11_3 : state_type := "00001101";
   CONSTANT s307 : STATE_TYPE := "00001001";
   constant G11_4 : state_type := "00001110";
   CONSTANT s177 : STATE_TYPE := "00001000";
   constant G11_5 : state_type := "00001111";
   CONSTANT s180 : STATE_TYPE := "00011000";
   constant G11_6 : state_type := "00010000";
   CONSTANT s181 : STATE_TYPE := "00011001";
   constant G11_7 : state_type := "00010001";
   CONSTANT s182 : STATE_TYPE := "00011011";
   constant G11_e : state_type := "00010010";
   CONSTANT s183 : STATE_TYPE := "00011010";
   constant G12_1 : state_type := "00010011";
   CONSTANT s184 : STATE_TYPE := "00011110";
   constant G12_e1 : state_type := "00010100";
   CONSTANT s185 : STATE_TYPE := "00011111";
   constant G12_e2 : state_type := "00010101";
   CONSTANT s186 : STATE_TYPE := "00011101";
   constant G13_1 : state_type := "00010110";
   CONSTANT s187 : STATE_TYPE := "00011100";
   constant G13_2 : state_type := "00010111";
   CONSTANT s188 : STATE_TYPE := "00010100";
   constant G13_e : state_type := "00011000";
   CONSTANT s189 : STATE_TYPE := "00010101";
   constant G14_1 : state_type := "00011001";
   CONSTANT s190 : STATE_TYPE := "00010111";
   constant G14_2 : state_type := "00011010";
   CONSTANT s191 : STATE_TYPE := "00010110";
   constant G14_3 : state_type := "00011011";
   CONSTANT s192 : STATE_TYPE := "00010010";
   constant G14_4 : state_type := "00011100";
   CONSTANT s193 : STATE_TYPE := "00010011";
   constant G14_5 : state_type := "00011101";
   CONSTANT s377 : STATE_TYPE := "00010001";
   constant G14_6 : state_type := "00011110";
   CONSTANT s381 : STATE_TYPE := "00010000";
   constant G14_7 : state_type := "00011111";
   CONSTANT s378 : STATE_TYPE := "00110000";
   constant G14_e : state_type := "00100000";
   CONSTANT s382 : STATE_TYPE := "00110001";
   constant G15_1 : state_type := "00100001";
   CONSTANT s379 : STATE_TYPE := "00110011";
   constant G15_2 : state_type := "00100010";
   CONSTANT s383 : STATE_TYPE := "00110010";
   constant G15_3 : state_type := "00100011";
   CONSTANT s384 : STATE_TYPE := "00110110";
   constant G15_4 : state_type := "00100100";
   CONSTANT s380 : STATE_TYPE := "00110111";
   constant G15_5 : state_type := "00100101";
   CONSTANT s385 : STATE_TYPE := "00110101";
   constant G15_6 : state_type := "00100110";
   CONSTANT s386 : STATE_TYPE := "00110100";
   constant G15_7 : state_type := "00100111";
   CONSTANT s387 : STATE_TYPE := "00111100";
   constant G15_e1 : state_type := "00101000";
   CONSTANT s388 : STATE_TYPE := "00111101";
   constant G15_e2 : state_type := "00101001";
   CONSTANT s389 : STATE_TYPE := "00111111";
   constant G15_e3 : state_type := "00101010";
   CONSTANT s391 : STATE_TYPE := "00111110";
   constant G16_1 : state_type := "00101011";
   CONSTANT s392 : STATE_TYPE := "00111010";
   constant G16_2 : state_type := "00101100";
   CONSTANT s390 : STATE_TYPE := "00111011";
   constant G16_3 : state_type := "00101101";
   CONSTANT s393 : STATE_TYPE := "00111001";
   constant G16_4 : state_type := "00101110";
   CONSTANT s394 : STATE_TYPE := "00111000";
   constant G16_5 : state_type := "00101111";
   CONSTANT s395 : STATE_TYPE := "00101000";
   constant G16_6 : state_type := "00110000";
   CONSTANT s396 : STATE_TYPE := "00101001";
   constant G16_7 : state_type := "00110001";
   CONSTANT s397 : STATE_TYPE := "00101011";
   constant G16_e1 : state_type := "00110010";
   CONSTANT s398 : STATE_TYPE := "00101010";
   constant G16_e2 : state_type := "00110011";
   CONSTANT s399 : STATE_TYPE := "00101110";
   constant G16_e3 : state_type := "00110100";
   CONSTANT s400 : STATE_TYPE := "00101111";
   constant G17_1 : state_type := "00110101";
   CONSTANT s401 : STATE_TYPE := "00101101";
   constant G17_10 : state_type := "00110110";
   CONSTANT s526 : STATE_TYPE := "00101100";
   constant G17_2 : state_type := "00110111";
   CONSTANT s527 : STATE_TYPE := "00100100";
   constant G17_3 : state_type := "00111000";
   CONSTANT s528 : STATE_TYPE := "00100101";
   constant G17_4 : state_type := "00111001";
   CONSTANT s529 : STATE_TYPE := "00100111";
   constant G17_5 : state_type := "00111010";
   CONSTANT s530 : STATE_TYPE := "00100110";
   constant G17_6 : state_type := "00111011";
   CONSTANT s531 : STATE_TYPE := "00100010";
   constant G17_7 : state_type := "00111100";
   CONSTANT s544 : STATE_TYPE := "00100011";
   constant G17_8 : state_type := "00111101";
   CONSTANT s545 : STATE_TYPE := "00100001";
   constant G17_9 : state_type := "00111110";
   CONSTANT s546 : STATE_TYPE := "00100000";
   constant G17_e : state_type := "00111111";
   CONSTANT s547 : STATE_TYPE := "01100000";
   constant G18_1 : state_type := "01000000";
   CONSTANT s549 : STATE_TYPE := "01100001";
   constant G18_2 : state_type := "01000001";
   CONSTANT s550 : STATE_TYPE := "01100011";
   constant G18_3 : state_type := "01000010";
   CONSTANT s404 : STATE_TYPE := "01100010";
   constant G18_4 : state_type := "01000011";
   CONSTANT s556 : STATE_TYPE := "01100110";
   constant G18_5 : state_type := "01000100";
   CONSTANT s557 : STATE_TYPE := "01100111";
   constant G18_e : state_type := "01000101";
   CONSTANT s579 : STATE_TYPE := "01100101";
   constant G19_1 : state_type := "01000110";
   CONSTANT s201 : STATE_TYPE := "01100100";
   constant G1_1 : state_type := "01000111";
   CONSTANT s202 : STATE_TYPE := "01101100";
   constant G20_1 : state_type := "01001000";
   CONSTANT s210 : STATE_TYPE := "01101101";
   constant G20_2 : state_type := "01001001";
   CONSTANT s211 : STATE_TYPE := "01101111";
   constant G20_3 : state_type := "01001010";
   CONSTANT s215 : STATE_TYPE := "01101110";
   constant G20_e : state_type := "01001011";
   CONSTANT s217 : STATE_TYPE := "01101010";
   constant G21_1 : state_type := "01001100";
   CONSTANT s218 : STATE_TYPE := "01101011";
   constant G21_2 : state_type := "01001101";
   CONSTANT s222 : STATE_TYPE := "01101001";
   constant G21_3 : state_type := "01001110";
   CONSTANT s223 : STATE_TYPE := "01101000";
   constant G21_4 : state_type := "01001111";
   CONSTANT s224 : STATE_TYPE := "01111000";
   constant G21_e : state_type := "01010000";
   CONSTANT s225 : STATE_TYPE := "01111001";
   constant G22_1 : state_type := "01010001";
   CONSTANT s226 : STATE_TYPE := "01111011";
   constant G22_e : state_type := "01010010";
   CONSTANT s243 : STATE_TYPE := "01111010";
   constant G23_1 : state_type := "01010011";
   CONSTANT s244 : STATE_TYPE := "01111110";
   constant G23_e : state_type := "01010100";
   CONSTANT s247 : STATE_TYPE := "01111111";
   constant G24_1 : state_type := "01010101";
   CONSTANT s344 : STATE_TYPE := "01111101";
   constant G24_2 : state_type := "01010110";
   CONSTANT s343 : STATE_TYPE := "01111100";
   constant G24_e : state_type := "01010111";
   CONSTANT s250 : STATE_TYPE := "01110100";
   constant G25_1 : state_type := "01011000";
   CONSTANT s251 : STATE_TYPE := "01110101";
   constant G25_2 : state_type := "01011001";
   CONSTANT s351 : STATE_TYPE := "01110111";
   constant G25_e : state_type := "01011010";
   CONSTANT s361 : STATE_TYPE := "01110110";
   constant G26_1 : state_type := "01011011";
   CONSTANT s360 : STATE_TYPE := "01110010";
   constant G26_2 : state_type := "01011100";
   CONSTANT s403 : STATE_TYPE := "01110011";
   constant G26_3 : state_type := "01011101";
   CONSTANT s406 : STATE_TYPE := "01110001";
   constant G26_4 : state_type := "01011110";
   CONSTANT s407 : STATE_TYPE := "01110000";
   constant G26_e : state_type := "01011111";
   CONSTANT s409 : STATE_TYPE := "01010000";
   constant G27_1 : state_type := "01100000";
   CONSTANT s412 : STATE_TYPE := "01010001";
   constant G27_2 : state_type := "01100001";
   CONSTANT s413 : STATE_TYPE := "01010011";
   constant G27_3 : state_type := "01100010";
   CONSTANT s416 : STATE_TYPE := "01010010";
   constant G27_4 : state_type := "01100011";
   CONSTANT s418 : STATE_TYPE := "01010110";
   constant G27_e : state_type := "01100100";
   CONSTANT s510 : STATE_TYPE := "01010111";
   constant G28_1 : state_type := "01100101";
   CONSTANT s553 : STATE_TYPE := "01010101";
   constant G28_2 : state_type := "01100110";
   CONSTANT s555 : STATE_TYPE := "01010100";
   constant G28_3 : state_type := "01100111";
   CONSTANT s558 : STATE_TYPE := "01011100";
   constant G28_4 : state_type := "01101000";
   CONSTANT s560 : STATE_TYPE := "01011101";
   constant G28_5 : state_type := "01101001";
   CONSTANT s561 : STATE_TYPE := "01011111";
   constant G28_e : state_type := "01101010";
   CONSTANT s563 : STATE_TYPE := "01011110";
   constant G29_1 : state_type := "01101011";
   CONSTANT s564 : STATE_TYPE := "01011010";
   constant G29_2 : state_type := "01101100";
   CONSTANT s565 : STATE_TYPE := "01011011";
   constant G29_3 : state_type := "01101101";
   CONSTANT s566 : STATE_TYPE := "01011001";
   constant G29_4 : state_type := "01101110";
   CONSTANT s266 : STATE_TYPE := "01011000";
   constant G29_5 : state_type := "01101111";
   CONSTANT s301 : STATE_TYPE := "01001000";
   constant G29_e : state_type := "01110000";
   CONSTANT s302 : STATE_TYPE := "01001001";
   constant G2_1 : state_type := "01110001";
   CONSTANT RES : STATE_TYPE := "01001011";
   constant G30_1 : state_type := "01110010";
   CONSTANT s511 : STATE_TYPE := "01001010";
   constant G30_2 : state_type := "01110011";
   CONSTANT s559 : STATE_TYPE := "01001110";
   constant G30_3 : state_type := "01110100";
   CONSTANT s562 : STATE_TYPE := "01001111";
   constant G30_4 : state_type := "01110101";
   CONSTANT s567 : STATE_TYPE := "01001101";
   constant G30_5 : state_type := "01110110";
   CONSTANT s568 : STATE_TYPE := "01001100";
   constant G30_e : state_type := "01110111";
   CONSTANT s569 : STATE_TYPE := "01000100";
   constant G31_1 : state_type := "01111000";
   CONSTANT s570 : STATE_TYPE := "01000101";
   constant G32_1 : state_type := "01111001";
   CONSTANT s571 : STATE_TYPE := "01000111";
   constant G33_1 : state_type := "01111010";
   CONSTANT s572 : STATE_TYPE := "01000110";
   constant G34_1 : state_type := "01111011";
   CONSTANT s573 : STATE_TYPE := "01000010";
   constant G3_1 : state_type := "01111100";
   CONSTANT s574 : STATE_TYPE := "01000011";
   constant G4_1 : state_type := "01111101";
   CONSTANT s548 : STATE_TYPE := "01000001";
   constant G5_1 : state_type := "01111110";
   CONSTANT s551 : STATE_TYPE := "01000000";
   constant G6_1 : state_type := "01111111";
   CONSTANT s552 : STATE_TYPE := "11000000";
   constant G7_1 : state_type := "10000000";
   CONSTANT s575 : STATE_TYPE := "11000001";
   constant G8_1 : state_type := "10000001";
   CONSTANT s576 : STATE_TYPE := "11000011";
   constant G9_1 : state_type := "10000010";
   CONSTANT s577 : STATE_TYPE := "11000010";
   constant RES : state_type := "10000011";
   CONSTANT s532 : STATE_TYPE := "11000110";
 
   CONSTANT s533 : STATE_TYPE := "11000111";
 
   CONSTANT s534 : STATE_TYPE := "11000101";
 
   CONSTANT s535 : STATE_TYPE := "11000100";
 
   CONSTANT s536 : STATE_TYPE := "11001100";
 
   CONSTANT s537 : STATE_TYPE := "11001101";
 
 
 
   -- Declare current and next state signals
   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE;
   signal current_state : state_type;
   SIGNAL next_state : STATE_TYPE;
   signal next_state : state_type;
 
 
   -- Declare any pre-registered internal signals
   -- Declare any pre-registered internal signals
   SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
   signal d_o_cld : std_logic_vector ( 7 downto 0 );
   SIGNAL rd_o_cld : std_logic ;
   signal rd_o_cld : std_logic ;
   SIGNAL sync_o_cld : std_logic ;
   signal sync_o_cld : std_logic ;
   SIGNAL wr_n_o_cld : std_logic ;
   signal wr_o_cld : std_logic ;
   SIGNAL wr_o_cld : std_logic ;
 
 
 
BEGIN
begin
 
 
   -----------------------------------------------------------------
   -----------------------------------------------------------------
   clocked_proc : PROCESS (
   clocked_proc : process (
      clk_clk_i,
      clk_clk_i,
      rst_rst_n_i
      rst_rst_n_i
   )
   )
   -----------------------------------------------------------------
   -----------------------------------------------------------------
   BEGIN
   begin
      IF (rst_rst_n_i = '0') THEN
      if (rst_rst_n_i = '0') then
         current_state <= RES;
         current_state <= RES;
         -- Default Reset Values
         -- Default Reset Values
         d_o_cld <= X"00";
         d_o_cld <= X"00";
         rd_o_cld <= '0';
         rd_o_cld <= '0';
         sync_o_cld <= '0';
         sync_o_cld <= '0';
         wr_n_o_cld <= '1';
 
         wr_o_cld <= '0';
         wr_o_cld <= '0';
         reg_F <= "00000100";
         reg_F <= "00000100";
         reg_sel_pc_in <= '0';
         reg_sel_pc_in <= '0';
         reg_sel_pc_val <= "00";
         reg_sel_pc_val <= "00";
         reg_sel_rb_in <= "00";
         reg_sel_rb_in <= "00";
Line 327... Line 316...
         zw_b1 <= X"00";
         zw_b1 <= X"00";
         zw_b2 <= X"00";
         zw_b2 <= X"00";
         zw_b3 <= X"00";
         zw_b3 <= X"00";
         zw_b4 <= X"00";
         zw_b4 <= X"00";
         zw_so <= '0';
         zw_so <= '0';
      ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
      elsif (clk_clk_i'event and clk_clk_i = '1') then
         current_state <= next_state;
         current_state <= next_state;
         -- Default Assignment To Internals
         -- Default Assignment To Internals
         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
         reg_sel_pc_in <= reg_sel_pc_in;
         reg_sel_pc_in <= reg_sel_pc_in;
         reg_sel_pc_val <= reg_sel_pc_val;
         reg_sel_pc_val <= reg_sel_pc_val;
Line 347... Line 336...
         zw_b2 <= zw_b2;
         zw_b2 <= zw_b2;
         zw_b3 <= zw_b3;
         zw_b3 <= zw_b3;
         zw_b4 <= zw_b4;
         zw_b4 <= zw_b4;
         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
         d_o_cld <= sig_D_OUT;
         d_o_cld <= sig_D_OUT;
         rd_o_cld <= sig_RD;
         rd_o_cld <= NOT(sig_WR);
         sync_o_cld <= sig_SYNC;
         sync_o_cld <= sig_SYNC;
         wr_n_o_cld <= sig_RWn;
 
         wr_o_cld <= sig_WR;
         wr_o_cld <= sig_WR;
 
 
         -- Combined Actions
         -- Combined Actions
         CASE current_state IS
         case current_state is
            WHEN FETCH =>
            when FETCH =>
               zw_REG_OP <= d_i;
               zw_REG_OP <= d_i;
               IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
               if ((nmi_i = '1') and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_REG_NMI <= '0';
                  zw_REG_NMI <= '0';
               ELSIF ((irq_n_i = '0' and
               elsif ((irq_n_i = '0' and
                      reg_F(2) = '0') AND (rdy_i = '1')) THEN
                      reg_F(2) = '0') and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"69" or
               elsif ((d_i = X"69" or
                      d_i = X"65" or
                      d_i = X"65" or
                      d_i = X"75" or
                      d_i = X"75" or
                      d_i = X"6D" or
                      d_i = X"6D" or
                      d_i = X"7D" or
                      d_i = X"7D" or
                      d_i = X"79" or
                      d_i = X"79" or
                      d_i = X"61" or
                      d_i = X"61" or
                      d_i = X"71") AND (rdy_i = '1')) THEN
                      d_i = X"71") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  zw_b1(0) <= reg_F(7);
                  zw_b1(0) <= reg_F(7);
               ELSIF ((d_i = X"06" or
               elsif ((d_i = X"06" or
                      d_i = X"16" or
                      d_i = X"16" or
                      d_i = X"0E" or
                      d_i = X"0E" or
                      d_i = X"1E") AND (rdy_i = '1')) THEN
                      d_i = X"1E") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"90" or
               elsif ((d_i = X"90" or
                      d_i = X"B0" or
                      d_i = X"B0" or
                      d_i = X"F0" or
                      d_i = X"F0" or
                      d_i = X"30" or
                      d_i = X"30" or
                      d_i = X"D0" or
                      d_i = X"D0" or
                      d_i = X"10" or
                      d_i = X"10" or
                      d_i = X"50" or
                      d_i = X"50" or
                      d_i = X"70") AND (rdy_i = '1')) THEN
                      d_i = X"70") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b3 <= adr_nxt_pc_i (15 downto 8);
                  zw_b3 <= adr_nxt_pc_i (15 downto 8);
               ELSIF ((d_i = X"24" or
               elsif ((d_i = X"24" or
                      d_i = X"2C") AND (rdy_i = '1')) THEN
                      d_i = X"2C") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"00") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"18") and (rdy_i = '1')) then
               ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"D8") and (rdy_i = '1')) then
               ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"58") and (rdy_i = '1')) then
               ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"B8") and (rdy_i = '1')) then
               ELSIF ((d_i = X"E0" or
               elsif ((d_i = X"E0" or
                      d_i = X"E4" or
                      d_i = X"E4" or
                      d_i = X"EC") AND (rdy_i = '1')) THEN
                      d_i = X"EC") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"C0" or
               elsif ((d_i = X"C0" or
                      d_i = X"C4" or
                      d_i = X"C4" or
                      d_i = X"CC") AND (rdy_i = '1')) THEN
                      d_i = X"CC") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "10";
                  reg_sel_rb_out <= "10";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"C6" or
               elsif ((d_i = X"C6" or
                      d_i = X"D6" or
                      d_i = X"D6" or
                      d_i = X"CE" or
                      d_i = X"CE" or
                      d_i = X"DE") AND (rdy_i = '1')) THEN
                      d_i = X"DE") and (rdy_i = '1')) then
                  zw_b4 <= X"FF";
                  zw_b4 <= X"FF";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"CA") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  zw_b4 <= X"FF";
                  zw_b4 <= X"FF";
               ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"88") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "10";
                  reg_sel_rb_out <= "10";
                  reg_sel_reg <= "10";
                  reg_sel_reg <= "10";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  zw_b4 <= X"FF";
                  zw_b4 <= X"FF";
               ELSIF ((d_i = X"49" or
               elsif ((d_i = X"49" or
                      d_i = X"45" or
                      d_i = X"45" or
                      d_i = X"55" or
                      d_i = X"55" or
                      d_i = X"4D" or
                      d_i = X"4D" or
                      d_i = X"5D" or
                      d_i = X"5D" or
                      d_i = X"59" or
                      d_i = X"59" or
Line 455... Line 443...
                      d_i = X"D5" or
                      d_i = X"D5" or
                      d_i = X"CD" or
                      d_i = X"CD" or
                      d_i = X"DD" or
                      d_i = X"DD" or
                      d_i = X"D9" or
                      d_i = X"D9" or
                      d_i = X"C1" or
                      d_i = X"C1" or
                      d_i = X"D1") AND (rdy_i = '1')) THEN
                      d_i = X"D1") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"E6" or
               elsif ((d_i = X"E6" or
                      d_i = X"F6" or
                      d_i = X"F6" or
                      d_i = X"EE" or
                      d_i = X"EE" or
                      d_i = X"FE") AND (rdy_i = '1')) THEN
                      d_i = X"FE") and (rdy_i = '1')) then
                  zw_b4 <= X"01";
                  zw_b4 <= X"01";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"E8") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  zw_b4 <= X"01";
                  zw_b4 <= X"01";
               ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"C8") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "10";
                  reg_sel_rb_out <= "10";
                  reg_sel_reg <= "10";
                  reg_sel_reg <= "10";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  zw_b4 <= X"01";
                  zw_b4 <= X"01";
               ELSIF ((d_i = X"4C" or
               elsif ((d_i = X"4C" or
                      d_i = X"6C") AND (rdy_i = '1')) THEN
                      d_i = X"6C") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"20") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"A9" or
               elsif ((d_i = X"A9" or
                      d_i = X"A5" or
                      d_i = X"A5" or
                      d_i = X"B5" or
                      d_i = X"B5" or
                      d_i = X"AD" or
                      d_i = X"AD" or
                      d_i = X"BD" or
                      d_i = X"BD" or
                      d_i = X"B9" or
                      d_i = X"B9" or
                      d_i = X"A1" or
                      d_i = X"A1" or
                      d_i = X"B1") AND (rdy_i = '1')) THEN
                      d_i = X"B1") and (rdy_i = '1')) then
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"A2" or
               elsif ((d_i = X"A2" or
                      d_i = X"A6" or
                      d_i = X"A6" or
                      d_i = X"B6" or
                      d_i = X"B6" or
                      d_i = X"AE" or
                      d_i = X"AE" or
                      d_i = X"BE") AND (rdy_i = '1')) THEN
                      d_i = X"BE") and (rdy_i = '1')) then
                  reg_sel_reg <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"A0" or
               elsif ((d_i = X"A0" or
                      d_i = X"A4" or
                      d_i = X"A4" or
                      d_i = X"B4" or
                      d_i = X"B4" or
                      d_i = X"AC" or
                      d_i = X"AC" or
                      d_i = X"BC") AND (rdy_i = '1')) THEN
                      d_i = X"BC") and (rdy_i = '1')) then
                  reg_sel_reg <= "10";
                  reg_sel_reg <= "10";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"46" or
               elsif ((d_i = X"46" or
                      d_i = X"56" or
                      d_i = X"56" or
                      d_i = X"4E" or
                      d_i = X"4E" or
                      d_i = X"5E") AND (rdy_i = '1')) THEN
                      d_i = X"5E") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"EA") and (rdy_i = '1')) then
               ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"48") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"08") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"68") and (rdy_i = '1')) then
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
 
 
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
               ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"28") and (rdy_i = '1')) then
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"26" or
               elsif ((d_i = X"26" or
                      d_i = X"36" or
                      d_i = X"36" or
                      d_i = X"2E" or
                      d_i = X"2E" or
                      d_i = X"3E") AND (rdy_i = '1')) THEN
                      d_i = X"3E") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"66" or
               elsif ((d_i = X"66" or
                      d_i = X"76" or
                      d_i = X"76" or
                      d_i = X"6E" or
                      d_i = X"6E" or
                      d_i = X"7E") AND (rdy_i = '1')) THEN
                      d_i = X"7E") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"40") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '0';
 
               elsif ((d_i = X"60") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"E9" or
               elsif ((d_i = X"E9" or
                      d_i = X"E5" or
                      d_i = X"E5" or
                      d_i = X"F5" or
                      d_i = X"F5" or
                      d_i = X"ED" or
                      d_i = X"ED" or
                      d_i = X"FD" or
                      d_i = X"FD" or
                      d_i = X"F9" or
                      d_i = X"F9" or
                      d_i = X"E1" or
                      d_i = X"E1" or
                      d_i = X"F1") AND (rdy_i = '1')) THEN
                      d_i = X"F1") and (rdy_i = '1')) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  zw_b1(0) <= reg_F(7);
                  zw_b1(0) <= reg_F(7);
               ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"38") and (rdy_i = '1')) then
               ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"F8") and (rdy_i = '1')) then
               ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"78") and (rdy_i = '1')) then
               ELSIF ((d_i = X"85" or
               elsif ((d_i = X"85" or
                      d_i = X"95" or
                      d_i = X"95" or
                      d_i = X"8D" or
                      d_i = X"8D" or
                      d_i = X"9D" or
                      d_i = X"9D" or
                      d_i = X"99" or
                      d_i = X"99" or
                      d_i = X"81" or
                      d_i = X"81" or
                      d_i = X"91") AND (rdy_i = '1')) THEN
                      d_i = X"91") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"86" or
               elsif ((d_i = X"86" or
                      d_i = X"96" or
                      d_i = X"96" or
                      d_i = X"8E") AND (rdy_i = '1')) THEN
                      d_i = X"8E") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"84" or
               elsif ((d_i = X"84" or
                      d_i = X"94" or
                      d_i = X"94" or
                      d_i = X"8C") AND (rdy_i = '1')) THEN
                      d_i = X"8C") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "10";
                  reg_sel_rb_out <= "10";
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
               ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"AA") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_rb_in <= "00";
                  reg_sel_rb_in <= "00";
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"0A") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
               ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"4A") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
               ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"2A") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
               ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"6A") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
               ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"A8") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "00";
                  reg_sel_rb_out <= "00";
                  reg_sel_reg <= "10";
                  reg_sel_reg <= "10";
                  reg_sel_rb_in <= "00";
                  reg_sel_rb_in <= "00";
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"98") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "10";
                  reg_sel_rb_out <= "10";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "01";
                  reg_sel_rb_in <= "01";
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"BA") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_reg <= "01";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"8A") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  reg_sel_reg <= "00";
                  reg_sel_reg <= "00";
                  reg_sel_rb_in <= "10";
                  reg_sel_rb_in <= "10";
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
               elsif ((d_i = X"9A") and (rdy_i = '1')) then
                  reg_sel_rb_out <= "01";
                  reg_sel_rb_out <= "01";
                  reg_sel_reg <= "11";
                  reg_sel_reg <= "11";
                  reg_sel_rb_in <= "11";
                  reg_sel_rb_in <= "11";
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_in <= '1';
                  reg_sel_sp_as <= '0';
                  reg_sel_sp_as <= '0';
               END IF;
               end if;
            WHEN s1 =>
            when G10_1 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1' and
                  sig_PC <= adr_pc_i;
                   zw_REG_OP = X"65") then
                  reg_sel_pc_in <= '0';
                  sig_PC <= X"00" & d_i;
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"69" and
 
                      reg_F(3) = '0') then
 
                  sig_PC <= adr_nxt_pc_i;
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               elsif (rdy_i = '1' and
            WHEN s2 =>
                      zw_REG_OP = X"75") then
               IF (rdy_i = '1') THEN
                  sig_PC <= X"00" & d_i;
                  sig_PC <= adr_pc_i;
                  zw_b1 <= d_alu_i;
                  reg_F(0) <= '1';
               elsif (rdy_i = '1' and
                  reg_sel_pc_in <= '0';
                      zw_REG_OP = X"6D") then
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_i;
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"7D") then
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"79") then
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"71") then
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"61") then
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"69" and
 
                      reg_F(3) = '1') then
 
                  sig_PC <= adr_nxt_pc_i;
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU4(4);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               end if;
            WHEN s5 =>
            when G10_2 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G10_3 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
               end if;
 
            when G10_4 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  zw_b3 <= d_alu_i;
 
               end if;
 
            when G10_5 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               end if;
 
            when G10_6 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  zw_b3 <= d_alu_i;
 
               end if;
 
            when G10_7 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G10_e1 =>
 
               if (rdy_i = '1' AND
 
                   zw_b2(0) = '0' and
 
                   reg_F(3) = '0') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(3) <= '1';
 
                  reg_sel_pc_in <= '0';
 
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               elsif (rdy_i = '1' AND
            WHEN s3 =>
                      zw_b2(0) = '0' and
               sig_PC <= adr_pc_i;
                      reg_F(3) = '1') then
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(2) <= '1';
 
                  reg_sel_pc_in <= '0';
 
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU4(4);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               elsif (rdy_i = '1') then
            WHEN s4 =>
                  sig_PC <= zw_b3 & zw_b1;
               IF (rdy_i = '1' and
               end if;
                   zw_REG_OP = X"9A") THEN
            when G10_e2 =>
 
               if (rdy_i = '1' and
 
                   reg_F(3) = '0') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_sel_pc_in <= '0';
 
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"BA") THEN
                      reg_F(3) = '1') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU4(4);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1') THEN
               end if;
                  sig_PC <= adr_pc_i;
            when G10_e3 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & d_alu_i;
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G11_1 =>
 
               if (rdy_i = '1' and
 
                   (zw_REG_OP = X"1E" or
 
                   zw_REG_OP = X"7E" or
 
                   zw_REG_OP = X"3E" or
 
                   zw_REG_OP = X"5E")) then
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               elsif (rdy_i = '1' and
 
                      (zw_REG_OP = X"06" or
 
                      zw_REG_OP = X"66" or
 
                      zw_REG_OP = X"26" or
 
                      zw_REG_OP = X"46")) then
 
                  sig_PC <= X"00" & d_i;
 
               elsif (rdy_i = '1' and
 
                      (zw_REG_OP = X"16" or
 
                      zw_REG_OP = X"76" or
 
                      zw_REG_OP = X"36" or
 
                      zw_REG_OP = X"56")) then
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               elsif (rdy_i = '1' and
 
                      (zw_REG_OP = X"0E" or
 
                      zw_REG_OP = X"6E" or
 
                      zw_REG_OP = X"2E" or
 
                      zw_REG_OP = X"4E")) then
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G11_2 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G11_4 =>
 
               if (rdy_i = '1' and
 
                   (zw_REG_OP = X"06" or
 
                   zw_REG_OP = X"16" or
 
                   zw_REG_OP = X"0E" or
 
                   zw_REG_OP = X"1E")) then
 
                  zw_b1 <= d_i(6 downto 0) & '0';
 
                  zw_b2(0) <= d_i(7);
 
               elsif (rdy_i = '1' and
 
                      (zw_REG_OP = X"46" or
 
                      zw_REG_OP = X"56" or
 
                      zw_REG_OP = X"4E" or
 
                      zw_REG_OP = X"5E")) then
 
                  zw_b1 <= '0' & d_i(7 downto 1);
 
                  zw_b2(0) <= d_i(0);
 
               elsif (rdy_i = '1' and
 
                      (zw_REG_OP = X"26" or
 
                      zw_REG_OP = X"36" or
 
                      zw_REG_OP = X"2E" or
 
                      zw_REG_OP = X"3E")) then
 
                  zw_b1 <= d_i(6 downto 0) & reg_F(0);
 
                  zw_b2(0) <= d_i(7);
 
               elsif (rdy_i = '1' and
 
                      (zw_REG_OP = X"66" or
 
                      zw_REG_OP = X"76" or
 
                      zw_REG_OP = X"6E" or
 
                      zw_REG_OP = X"7E")) then
 
                  zw_b1 <= reg_F(0) & d_i(7 downto 1);
 
                  zw_b2(0) <= d_i(0);
 
               end if;
 
            when G11_5 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
               end if;
 
            when G11_6 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  zw_b3 <= d_alu_i;
 
               end if;
 
            when G11_7 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= zw_b3 & zw_b1;
 
               end if;
 
            when G11_e =>
 
               reg_F(0) <= zw_b2(0);
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s12 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(0) <= '0';
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
            when G12_1 =>
            WHEN s16 =>
               if (rdy_i = '1' and (
               IF (rdy_i = '1') THEN
                   (reg_F(0) = '1' and zw_REG_OP = X"90") or
                  sig_PC <= adr_pc_i;
                   (reg_F(0) = '0' and zw_REG_OP = X"B0") or
                  reg_F(3) <= '0';
                   (reg_F(1) = '0' and zw_REG_OP = X"F0") or
 
                   (reg_F(7) = '0' and zw_REG_OP = X"30") or
 
                   (reg_F(1) = '1' and zw_REG_OP = X"D0") or
 
                   (reg_F(7) = '1' and zw_REG_OP = X"10") or
 
                   (reg_F(6) = '1' and zw_REG_OP = X"50") or
 
                   (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
 
                  sig_PC <= adr_nxt_pc_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               elsif (rdy_i = '1') then
            WHEN s17 =>
                  sig_PC <= adr_nxt_pc_i;
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(2) <= '0';
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "10";
                  reg_sel_pc_val <= "00";
                  zw_b2 <= d_i;
                  reg_sel_sp_in <= '0';
               end if;
                  reg_sel_sp_as <= '1';
            when G12_e1 =>
               END IF;
               if (rdy_i = '1' and
            WHEN s24 =>
                   zw_b3 = adr_nxt_pc_i (15 downto 8)) then
               IF (rdy_i = '1') THEN
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_pc_i;
 
                  reg_F(6) <= '0';
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               elsif (rdy_i = '1') then
            WHEN s25 =>
                  sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
               IF (rdy_i = '1') THEN
               end if;
 
            when G12_e2 =>
 
               if (rdy_i = '1') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               end if;
            WHEN s271 =>
            when G13_1 =>
               IF (rdy_i = '1' and
               if (rdy_i = '1' and
                   zw_REG_OP = X"4C") THEN
                   zw_REG_OP = X"24") then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= X"00" & d_i;
                  reg_sel_pc_in <= '1';
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"2C") then
                  reg_sel_pc_val <= "11";
 
                  zw_b1 <= d_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"6C") THEN
 
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_sel_pc_in <= '1';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s273 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  zw_b2 <= d_i;
 
               END IF;
 
            WHEN s304 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
 
                  reg_sel_pc_in <= '1';
 
 
 
                  reg_sel_pc_val <= "11";
 
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               END IF;
               end if;
            WHEN s307 =>
            when G13_2 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
 
               end if;
 
            when G13_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= d_i(7);
 
                  reg_F(6) <= d_i(6);
 
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               end if;
            WHEN s177 =>
            when G14_1 =>
               IF (rdy_i = '1' and
               if (rdy_i = '1' and
                   (zw_REG_OP = X"85" OR
                   (zw_REG_OP = X"C6" OR
                   zw_REG_OP = X"86" OR
                   zw_REG_OP = X"E6")) then
                   zw_REG_OP = X"84")) THEN
 
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"95" OR
                      (zw_REG_OP = X"D6" OR
                      zw_REG_OP = X"94")) THEN
                      zw_REG_OP = X"F6")) then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"8D" OR
                      (zw_REG_OP = X"CE" OR
                      zw_REG_OP = X"8E" OR
                      zw_REG_OP = X"EE")) then
                      zw_REG_OP = X"8C")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"9D") THEN
                      (zw_REG_OP = X"DE" OR
                  sig_PC <= adr_nxt_pc_i;
                      zw_REG_OP = X"FE")) then
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"99") THEN
 
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               ELSIF (rdy_i = '1' and
               end if;
                      zw_REG_OP = X"91") THEN
            when G14_2 =>
                  sig_PC <= X"00" & d_i;
               if (rdy_i = '1') then
                  zw_b1 <= d_alu_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"81") THEN
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"96") THEN
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               END IF;
 
            WHEN s180 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
                  zw_b3 <= d_alu_i;
 
               END IF;
 
            WHEN s181 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & zw_b1;
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G14_3 =>
 
               if (rdy_i = '1') then
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
               end if;
               END IF;
            when G14_5 =>
            WHEN s182 =>
               if (rdy_i = '1') then
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
               end if;
               END IF;
            when G14_6 =>
            WHEN s183 =>
               if (rdy_i = '1') then
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
               END IF;
                  zw_b3 <= d_alu_i;
            WHEN s184 =>
               end if;
 
            when G14_7 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= zw_b3 & zw_b1;
 
               end if;
 
            when G14_e =>
 
               reg_F(7) <= reg_7flag_i;
 
               reg_F(1) <= reg_1flag_i;
               sig_PC <= adr_pc_i;
               sig_PC <= adr_pc_i;
               reg_sel_pc_in <= '0';
               reg_sel_pc_in <= '0';
 
 
               reg_sel_pc_val <= "00";
               reg_sel_pc_val <= "00";
               reg_sel_sp_in <= '0';
               reg_sel_sp_in <= '0';
               reg_sel_sp_as <= '1';
               reg_sel_sp_as <= '1';
            WHEN s185 =>
            when G15_1 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1' and
                  sig_PC <= X"00" & zw_b1;
                   (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
               END IF;
                   zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
            WHEN s186 =>
                   zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
               IF (rdy_i = '1') THEN
                   zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
                  sig_PC <= X"00" & zw_b1;
                  sig_PC <= X"00" & d_i;
               END IF;
               elsif ((rdy_i = '1' and
            WHEN s187 =>
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
               sig_PC <= adr_pc_i;
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
 
                      zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
 
                      zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
 
                      zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
 
                  sig_PC <= adr_nxt_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
               reg_sel_pc_in <= '0';
               reg_sel_pc_in <= '0';
 
 
               reg_sel_pc_val <= "00";
               reg_sel_pc_val <= "00";
               reg_sel_sp_in <= '0';
               reg_sel_sp_in <= '0';
               reg_sel_sp_as <= '1';
               reg_sel_sp_as <= '1';
            WHEN s188 =>
               elsif ((rdy_i = '1' and
               IF (rdy_i = '1') THEN
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                  sig_PC <= X"00" & d_alu_i;
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                  zw_b1 <= d_i;
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
               END IF;
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
            WHEN s189 =>
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
               IF (rdy_i = '1') THEN
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= d_i & zw_b1;
                  reg_F(7) <= reg_7flag_i;
                  zw_b3 <= d_alu_i;
                  reg_F(1) <= reg_1flag_i;
               END IF;
 
            WHEN s190 =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '0';
               reg_sel_pc_in <= '0';
 
 
               reg_sel_pc_val <= "00";
               reg_sel_pc_val <= "00";
               reg_sel_sp_in <= '0';
               reg_sel_sp_in <= '0';
               reg_sel_sp_as <= '1';
               reg_sel_sp_as <= '1';
            WHEN s191 =>
               elsif ((rdy_i = '1' and
               sig_PC <= zw_b3 & zw_b1;
 
            WHEN s192 =>
 
               sig_PC <= d_i & zw_b1;
 
            WHEN s193 =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '0';
 
 
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            WHEN s377 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s381 =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '0';
 
 
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            WHEN s378 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s382 =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '0';
 
 
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            WHEN s383 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s384 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s385 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s386 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F <= d_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s387 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s388 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s389 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
                  reg_F <= d_i;
 
                  reg_sel_pc_in <= '1';
 
 
 
                  reg_sel_pc_val <= "11";
 
               END IF;
 
            WHEN s391 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s392 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s390 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s393 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s394 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
                  zw_b1 <= d_i;
 
                  reg_sel_pc_in <= '1';
 
 
 
                  reg_sel_pc_val <= "00";
 
               END IF;
 
            WHEN s395 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
               END IF;
 
            WHEN s396 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s397 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s399 =>
 
               sig_PC <= adr_sp_i;
 
            WHEN s400 =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '1';
 
 
 
               reg_sel_pc_val <= "11";
 
            WHEN s401 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1 (7 downto 0);
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s526 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_sp_i;
 
               END IF;
 
            WHEN s527 =>
 
               sig_PC <= adr_sp_i;
 
            WHEN s528 =>
 
               sig_PC <= adr_sp_i;
 
            WHEN s529 =>
 
               sig_PC <= X"FFFE";
 
            WHEN s530 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_F(2) <= '1';
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s531 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"FFFF";
 
                  reg_sel_pc_in <= '1';
 
 
 
                  reg_sel_pc_val <= "11";
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s544 =>
 
               sig_PC <= adr_sp_i;
 
            WHEN s545 =>
 
               sig_PC <= adr_sp_i;
 
               reg_sel_pc_in <= '0';
 
 
 
               reg_sel_pc_val <= "00";
 
            WHEN s546 =>
 
               sig_PC <= adr_pc_i;
 
            WHEN s547 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  zw_b1 <= d_i;
 
                  reg_sel_pc_in <= '1';
 
 
 
                  reg_sel_pc_val <= "11";
 
               END IF;
 
            WHEN s549 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC  <= d_i & zw_b1;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s550 =>
 
               sig_PC <= adr_sp_i;
 
               reg_sel_pc_in <= '1';
 
 
 
               reg_sel_pc_val <= "00";
 
            WHEN s404 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(7);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s556 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(0);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s557 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(7);
 
                  reg_F(0) <= q_a_i(7);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s579 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(0);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s201 =>
 
               IF (rdy_i = '1' and
 
                   (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
 
                   zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
 
                   zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
 
                   zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
 
                  sig_PC <= X"00" & d_i;
 
               ELSIF ((rdy_i = '1' and
 
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
 
                      zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
 
                      zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
 
                      zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               ELSIF ((rdy_i = '1' and
 
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
 
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
 
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
 
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               ELSIF ((rdy_i = '1' and
 
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1' and
               elsif ((rdy_i = '1' and
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(0) <= zw_ALU(8);
                  reg_F(0) <= zw_ALU(8);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"B5" OR
                      (zw_REG_OP = X"B5" OR
                      zw_REG_OP = X"B4" OR
                      zw_REG_OP = X"B4" OR
                      zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
                      zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
                      zw_REG_OP = X"35" OR
                      zw_REG_OP = X"35" OR
                      zw_REG_OP = X"D5")) THEN
                      zw_REG_OP = X"D5")) then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"AD" OR
                      (zw_REG_OP = X"AD" OR
                      zw_REG_OP = X"AE" OR
                      zw_REG_OP = X"AE" OR
                      zw_REG_OP = X"AC" OR
                      zw_REG_OP = X"AC" OR
                      zw_REG_OP = X"4D" OR
                      zw_REG_OP = X"4D" OR
                      zw_REG_OP = X"0D" OR
                      zw_REG_OP = X"0D" OR
                      zw_REG_OP = X"2D" OR
                      zw_REG_OP = X"2D" OR
                      zw_REG_OP = X"CD" OR
                      zw_REG_OP = X"CD" OR
                      zw_REG_OP = X"EC" OR
                      zw_REG_OP = X"EC" OR
                      zw_REG_OP = X"CC")) THEN
                      zw_REG_OP = X"CC")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"BD" OR
                      (zw_REG_OP = X"BD" OR
                      zw_REG_OP = X"BC" OR
                      zw_REG_OP = X"BC" OR
                      zw_REG_OP = X"5D" OR
                      zw_REG_OP = X"5D" OR
                      zw_REG_OP = X"1D" OR
                      zw_REG_OP = X"1D" OR
                      zw_REG_OP = X"3D" OR
                      zw_REG_OP = X"3D" OR
                      zw_REG_OP = X"DD")) THEN
                      zw_REG_OP = X"DD")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"B9" OR
                      (zw_REG_OP = X"B9" OR
                      zw_REG_OP = X"BE" OR
                      zw_REG_OP = X"BE" OR
                      zw_REG_OP = X"59" OR
                      zw_REG_OP = X"59" OR
                      zw_REG_OP = X"19" OR
                      zw_REG_OP = X"19" OR
                      zw_REG_OP = X"39" OR
                      zw_REG_OP = X"39" OR
                      zw_REG_OP = X"D9")) THEN
                      zw_REG_OP = X"D9")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"B1" OR
                      (zw_REG_OP = X"B1" OR
                      zw_REG_OP = X"51" OR
                      zw_REG_OP = X"51" OR
                      zw_REG_OP = X"11" OR
                      zw_REG_OP = X"11" OR
                      zw_REG_OP = X"31" OR
                      zw_REG_OP = X"31" OR
                      zw_REG_OP = X"D1")) THEN
                      zw_REG_OP = X"D1")) then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"A1" OR
                      (zw_REG_OP = X"A1" OR
                      zw_REG_OP = X"41" OR
                      zw_REG_OP = X"41" OR
                      zw_REG_OP = X"01" OR
                      zw_REG_OP = X"01" OR
                      zw_REG_OP = X"21" OR
                      zw_REG_OP = X"21" OR
                      zw_REG_OP = X"C1")) THEN
                      zw_REG_OP = X"C1")) then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"B6") THEN
                      zw_REG_OP = X"B6") then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               END IF;
               end if;
            WHEN s202 =>
            when G15_2 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= X"00" & zw_b1;
               END IF;
               end if;
            WHEN s210 =>
            when G15_3 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
               end if;
               END IF;
            when G15_4 =>
            WHEN s211 =>
               if (rdy_i = '1') then
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
                  zw_b3 <= d_alu_i;
               END IF;
               end if;
            WHEN s215 =>
            when G15_5 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= X"00" & zw_b1;
                  sig_PC <= X"00" & zw_b1;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               END IF;
               end if;
            WHEN s217 =>
            when G15_6 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= X"00" & zw_b1;
 
               END IF;
 
            WHEN s218 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & zw_b1;
 
               END IF;
 
            WHEN s222 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & d_alu_i;
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s223 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
                  zw_b3 <= d_alu_i;
               END IF;
               end if;
            WHEN s224 =>
            when G15_7 =>
               IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G15_e1 =>
 
               if ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
               elsif ((rdy_i = '1' AND
 
                      zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
               elsif ((rdy_i = '1' AND
 
                      zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
               elsif ((rdy_i = '1' AND
 
                      zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(0) <= zw_ALU(8);
                  reg_F(0) <= zw_ALU(8);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1') THEN
               elsif (rdy_i = '1' AND
 
                      zw_b2(0) = '0') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               elsif (rdy_i = '1') then
            WHEN s225 =>
                  sig_PC <= zw_b3 & zw_b1;
               IF ((rdy_i = '1' AND
               end if;
                   zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
            when G15_e2 =>
 
               if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1' AND
               elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                      zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
 
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1' AND
               elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                      zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
 
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF ((rdy_i = '1' AND
               elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                      zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
 
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(0) <= zw_ALU(8);
                  reg_F(0) <= zw_ALU(8);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' AND
               elsif (rdy_i = '1') then
                      zw_b2(0) = '0') THEN
 
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= reg_7flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_F(1) <= reg_1flag_i;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1') THEN
               end if;
                  sig_PC <= zw_b3 & zw_b1;
            when G15_e3 =>
               END IF;
               if (rdy_i = '1') then
            WHEN s226 =>
                  sig_PC <= X"00" & d_alu_i;
               IF (rdy_i = '1' and
                  zw_b1 <= d_i;
                   (zw_REG_OP = X"C6" OR
               end if;
                   zw_REG_OP = X"E6")) THEN
            when G16_1 =>
 
               if (rdy_i = '1' and
 
                   zw_REG_OP = X"E5") then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"D6" OR
                      zw_REG_OP = X"E9" and
                      zw_REG_OP = X"F6")) THEN
                      reg_F(3) = '0') then
 
                  sig_PC <= adr_nxt_pc_i;
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"F5") then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"CE" OR
                      zw_REG_OP = X"ED") then
                      zw_REG_OP = X"EE")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      (zw_REG_OP = X"DE" OR
                      zw_REG_OP = X"FD") then
                      zw_REG_OP = X"FE")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               END IF;
               elsif (rdy_i = '1' and
            WHEN s243 =>
                      zw_REG_OP = X"F9") then
               IF (rdy_i = '1') THEN
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= d_i & zw_b1;
 
               END IF;
 
            WHEN s244 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
                  zw_b3 <= d_alu_i;
 
               END IF;
 
            WHEN s247 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & zw_b1;
 
               END IF;
 
            WHEN s344 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= zw_b3 & zw_b1;
 
               END IF;
 
            WHEN s343 =>
 
               IF (rdy_i = '1') THEN
 
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               END IF;
                  zw_b2(0) <= reg_0flag_i;
            WHEN s251 =>
               elsif (rdy_i = '1' and
               sig_PC <= adr_pc_i;
                      zw_REG_OP = X"F1") then
               reg_F(7) <= reg_7flag_i;
                  sig_PC <= X"00" & d_i;
               reg_F(1) <= reg_1flag_i;
                  zw_b1 <= d_alu_i;
               reg_sel_pc_in <= '0';
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"E1") then
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            WHEN s351 =>
 
               IF (rdy_i = '1' and
 
                   zw_REG_OP = X"24") THEN
 
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
               ELSIF (rdy_i = '1' and
                  zw_b1 <= d_alu_i;
                      zw_REG_OP = X"2C") THEN
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"E9" and
 
                      reg_F(3) = '1') then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s361 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= d_i(7);
 
                  reg_F(6) <= d_i(6);
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU2(4);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               end if;
            WHEN s360 =>
            when G16_2 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G16_3 =>
 
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
               END IF;
               end if;
            WHEN s403 =>
            when G16_4 =>
               IF (rdy_i = '1' and
               if (rdy_i = '1') then
                   (zw_REG_OP = X"1E" or
 
                   zw_REG_OP = X"7E" or
 
                   zw_REG_OP = X"3E" or
 
                   zw_REG_OP = X"5E")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               ELSIF (rdy_i = '1' and
 
                      (zw_REG_OP = X"06" or
 
                      zw_REG_OP = X"66" or
 
                      zw_REG_OP = X"26" or
 
                      zw_REG_OP = X"46")) THEN
 
                  sig_PC <= X"00" & d_i;
 
               ELSIF (rdy_i = '1' and
 
                      (zw_REG_OP = X"16" or
 
                      zw_REG_OP = X"76" or
 
                      zw_REG_OP = X"36" or
 
                      zw_REG_OP = X"56")) THEN
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               ELSIF (rdy_i = '1' and
 
                      (zw_REG_OP = X"0E" or
 
                      zw_REG_OP = X"6E" or
 
                      zw_REG_OP = X"2E" or
 
                      zw_REG_OP = X"4E")) THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s406 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
               END IF;
 
            WHEN s407 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
                  zw_b3 <= d_alu_i;
               END IF;
               end if;
            WHEN s409 =>
            when G16_5 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= X"00" & zw_b1;
                  sig_PC <= X"00" & zw_b1;
               END IF;
 
            WHEN s412 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= zw_b3 & zw_b1;
 
               END IF;
 
            WHEN s416 =>
 
               IF (rdy_i = '1' and
 
                   (zw_REG_OP = X"06" or
 
                   zw_REG_OP = X"16" or
 
                   zw_REG_OP = X"0E" or
 
                   zw_REG_OP = X"1E")) THEN
 
                  zw_b1 <= d_i(6 downto 0) & '0';
 
                  zw_b2(0) <= d_i(7);
 
               ELSIF (rdy_i = '1' and
 
                      (zw_REG_OP = X"46" or
 
                      zw_REG_OP = X"56" or
 
                      zw_REG_OP = X"4E" or
 
                      zw_REG_OP = X"5E")) THEN
 
                  zw_b1 <= '0' & d_i(7 downto 1);
 
                  zw_b2(0) <= d_i(0);
 
               ELSIF (rdy_i = '1' and
 
                      (zw_REG_OP = X"26" or
 
                      zw_REG_OP = X"36" or
 
                      zw_REG_OP = X"2E" or
 
                      zw_REG_OP = X"3E")) THEN
 
                  zw_b1 <= d_i(6 downto 0) & reg_F(0);
 
                  zw_b2(0) <= d_i(7);
 
               ELSIF (rdy_i = '1' and
 
                      (zw_REG_OP = X"66" or
 
                      zw_REG_OP = X"76" or
 
                      zw_REG_OP = X"6E" or
 
                      zw_REG_OP = X"7E")) THEN
 
                  zw_b1 <= reg_F(0) & d_i(7 downto 1);
 
                  zw_b2(0) <= d_i(0);
 
               END IF;
 
            WHEN s418 =>
 
               sig_PC <= adr_pc_i;
 
               reg_F(0) <= zw_b2(0);
 
               reg_F(7) <= reg_7flag_i;
 
               reg_F(1) <= reg_1flag_i;
 
               reg_sel_pc_in <= '0';
 
 
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            WHEN s510 =>
 
               IF (rdy_i = '1' and
 
                   zw_REG_OP = X"65") THEN
 
                  sig_PC <= X"00" & d_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"69" and
 
                      reg_F(3) = '0') THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"75") THEN
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"6D") THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"7D") THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"79") THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               ELSIF (rdy_i = '1' and
               end if;
                      zw_REG_OP = X"71") THEN
            when G16_6 =>
                  sig_PC <= X"00" & d_i;
               if (rdy_i = '1') then
                  zw_b1 <= d_alu_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"61") THEN
 
                  sig_PC <= X"00" & d_i;
 
                  zw_b1 <= d_alu_i;
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"69" and
 
                      reg_F(3) = '1') THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU4(4);
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s553 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
               END IF;
 
            WHEN s555 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
                  zw_b3 <= d_alu_i;
               END IF;
               end if;
            WHEN s558 =>
            when G16_7 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= X"00" & zw_b1;
 
                  zw_b1 <= d_alu_i;
 
                  zw_b2(0) <= reg_0flag_i;
 
               END IF;
 
            WHEN s560 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & zw_b1;
 
               END IF;
 
            WHEN s561 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & zw_b1;
                  sig_PC <= X"00" & zw_b1;
               END IF;
               end if;
            WHEN s563 =>
            when G16_e1 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1' AND
                  sig_PC <= X"00" & d_alu_i;
 
                  zw_b1 <= d_i;
 
               END IF;
 
            WHEN s564 =>
 
               IF (rdy_i = '1' AND
 
                   zw_b2(0) = '0' and
                   zw_b2(0) = '0' and
                   reg_F(3) = '0') THEN
                   reg_F(3) = '0') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
 
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_F(0) <= zw_ALU(8);
                  reg_F(0) <= zw_ALU(8);
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' AND
               elsif (rdy_i = '1' AND
                      zw_b2(0) = '0' and
                      zw_b2(0) = '0' and
                      reg_F(3) = '1') THEN
                      reg_F(3) = '1') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
 
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_F(0) <= zw_ALU4(4);
                  reg_F(0) <= zw_ALU2(4);
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1') THEN
               elsif (rdy_i = '1') then
                  sig_PC <= zw_b3 & zw_b1;
                  sig_PC <= zw_b3 & zw_b1;
               END IF;
               end if;
            WHEN s565 =>
            when G16_e2 =>
               IF (rdy_i = '1' and
               if (rdy_i = '1' and
                   reg_F(3) = '0') THEN
                   reg_F(3) = '0') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
 
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_F(0) <= zw_ALU(8);
                  reg_F(0) <= zw_ALU(8);
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      reg_F(3) = '1') THEN
                      reg_F(3) = '1') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
 
                  reg_F(7) <= zw_ALU(7);
                  reg_F(7) <= zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
                  (zw_ALU(0)));
                  (zw_ALU(0)));
                  reg_F(0) <= zw_ALU4(4);
                  reg_F(0) <= zw_ALU2(4);
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s566 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
 
                  zw_b3 <= d_alu_i;
 
               END IF;
 
            WHEN s266 =>
 
               IF (rdy_i = '1' and (
 
                   (reg_F(0) = '1' and zw_REG_OP = X"90") or
 
                   (reg_F(0) = '0' and zw_REG_OP = X"B0") or
 
                   (reg_F(1) = '0' and zw_REG_OP = X"F0") or
 
                   (reg_F(7) = '0' and zw_REG_OP = X"30") or
 
                   (reg_F(1) = '1' and zw_REG_OP = X"D0") or
 
                   (reg_F(7) = '1' and zw_REG_OP = X"10") or
 
                   (reg_F(6) = '1' and zw_REG_OP = X"50") or
 
                   (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               ELSIF (rdy_i = '1') THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "10";
 
                  zw_b2 <= d_i;
 
               END IF;
 
            WHEN s301 =>
 
               IF (rdy_i = '1' and
 
                   zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
 
                  sig_PC <= adr_nxt_pc_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               ELSIF (rdy_i = '1') THEN
 
                  sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
 
               END IF;
 
            WHEN s302 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= adr_pc_i;
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN RES =>
 
               reg_sel_pc_in <= '0';
 
               reg_sel_pc_val <= "00";
 
               sig_PC <= adr_nxt_pc_i;
 
               reg_sel_pc_in <= '0';
               reg_sel_pc_in <= '0';
 
 
               reg_sel_pc_val <= "00";
               reg_sel_pc_val <= "00";
               reg_sel_sp_in <= '0';
               reg_sel_sp_in <= '0';
               reg_sel_sp_as <= '1';
               reg_sel_sp_as <= '1';
            WHEN s511 =>
               end if;
               IF (rdy_i = '1' and
            when G16_e3 =>
                   zw_REG_OP = X"E5") THEN
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & d_alu_i;
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G17_1 =>
 
               if (rdy_i = '1' and
 
                   (zw_REG_OP = X"85" OR
 
                   zw_REG_OP = X"86" OR
 
                   zw_REG_OP = X"84")) then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"E9" and
                      (zw_REG_OP = X"95" OR
                      reg_F(3) = '0') THEN
                      zw_REG_OP = X"94")) then
                  sig_PC <= adr_nxt_pc_i;
 
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               ELSIF (rdy_i = '1' and
 
                      zw_REG_OP = X"F5") THEN
 
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"ED") THEN
                      (zw_REG_OP = X"8D" OR
 
                      zw_REG_OP = X"8E" OR
 
                      zw_REG_OP = X"8C")) then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"FD") THEN
                      zw_REG_OP = X"9D") then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"F9") THEN
                      zw_REG_OP = X"99") then
                  sig_PC <= adr_nxt_pc_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"F1") THEN
                      zw_REG_OP = X"91") then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"E1") THEN
                      zw_REG_OP = X"81") then
                  sig_PC <= X"00" & d_i;
                  sig_PC <= X"00" & d_i;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
               ELSIF (rdy_i = '1' and
               elsif (rdy_i = '1' and
                      zw_REG_OP = X"E9" and
                      zw_REG_OP = X"96") then
                      reg_F(3) = '1') THEN
                  sig_PC <= X"00" & d_i;
                  sig_PC <= adr_nxt_pc_i;
                  zw_b1 <= d_alu_i;
 
               end if;
                  reg_F(7) <= zw_ALU(7);
            when G17_10 =>
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU2(4);
 
                  reg_sel_pc_in <= '0';
 
 
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               END IF;
 
            WHEN s559 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
               END IF;
            when G17_2 =>
            WHEN s562 =>
               if (rdy_i = '1') then
               IF (rdy_i = '1') THEN
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G17_3 =>
 
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
               end if;
               END IF;
            when G17_4 =>
            WHEN s567 =>
               if (rdy_i = '1') then
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
                  zw_b3 <= d_alu_i;
               END IF;
               end if;
            WHEN s568 =>
            when G17_5 =>
               IF (rdy_i = '1') THEN
               sig_PC <= zw_b3 & zw_b1;
 
            when G17_6 =>
 
               if (rdy_i = '1') then
                  sig_PC <= X"00" & zw_b1;
                  sig_PC <= X"00" & zw_b1;
                  zw_b1 <= d_alu_i;
                  zw_b1 <= d_alu_i;
                  zw_b2(0) <= reg_0flag_i;
                  zw_b2(0) <= reg_0flag_i;
               END IF;
               end if;
            WHEN s569 =>
            when G17_7 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
                  sig_PC <= X"00" & zw_b1;
 
               END IF;
 
            WHEN s570 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"00" & zw_b1;
 
               END IF;
 
            WHEN s571 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  zw_b3 <= d_alu_i;
                  zw_b3 <= d_alu_i;
               END IF;
               end if;
            WHEN s572 =>
            when G17_8 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
 
                  sig_PC <= X"00" & zw_b1;
 
               end if;
 
            when G17_9 =>
 
               if (rdy_i = '1') then
                  sig_PC <= X"00" & d_alu_i;
                  sig_PC <= X"00" & d_alu_i;
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               END IF;
               end if;
            WHEN s573 =>
            when G17_e =>
               IF (rdy_i = '1' AND
 
                   zw_b2(0) = '0' and
 
                   reg_F(3) = '0') THEN
 
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' AND
            when G18_1 =>
                      zw_b2(0) = '0' and
               if (rdy_i = '1') then
                      reg_F(3) = '1') THEN
                  sig_PC <= adr_sp_i;
                  sig_PC <= adr_pc_i;
               end if;
 
            when G18_2 =>
                  reg_F(7) <= zw_ALU(7);
               sig_PC <= adr_sp_i;
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
            when G18_3 =>
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
               sig_PC <= adr_sp_i;
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
            when G18_4 =>
                  (zw_ALU(0)));
               sig_PC <= X"FFFE";
                  reg_F(0) <= zw_ALU2(4);
            when G18_5 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= X"FFFF";
 
                  reg_sel_pc_in <= '1';
 
                  reg_sel_pc_val <= "11";
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G18_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_F(2) <= '1';
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1') THEN
               end if;
                  sig_PC <= zw_b3 & zw_b1;
            when G19_1 =>
               END IF;
               if (rdy_i = '1') then
            WHEN s574 =>
 
               IF (rdy_i = '1' and
 
                   reg_F(3) = '0') THEN
 
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
                  reg_F(7) <= zw_ALU(7);
                  reg_F(1) <= reg_1flag_i;
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU(8);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               ELSIF (rdy_i = '1' and
               end if;
                      reg_F(3) = '1') THEN
            when G1_1 =>
 
               if (rdy_i = '1') then
                  sig_PC <= adr_pc_i;
                  sig_PC <= adr_pc_i;
 
 
                  reg_F(7) <= zw_ALU(7);
 
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
 
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
 
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
 
                  (zw_ALU(0)));
 
                  reg_F(0) <= zw_ALU2(4);
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               end if;
            WHEN s548 =>
            when G20_1 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1' and
                  sig_PC <= adr_sp_i;
                   zw_REG_OP = X"4C") then
               END IF;
                  sig_PC <= adr_nxt_pc_i;
            WHEN s551 =>
                  reg_sel_pc_in <= '1';
               sig_PC <= adr_sp_i;
                  reg_sel_pc_val <= "11";
            WHEN s552 =>
 
               sig_PC <= adr_sp_i;
 
            WHEN s575 =>
 
               IF (rdy_i = '1') THEN
 
                  sig_PC <= X"FFFF";
 
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               END IF;
               elsif (rdy_i = '1' and
            WHEN s576 =>
                      zw_REG_OP = X"6C") then
               sig_PC <= X"FFFE";
                  sig_PC <= adr_nxt_pc_i;
            WHEN s577 =>
                  reg_sel_pc_in <= '1';
               IF (rdy_i = '1') THEN
                  reg_sel_pc_val <= "00";
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G20_2 =>
 
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  reg_F(2) <= '1';
 
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  zw_b2 <= d_i;
                  reg_sel_sp_as <= '1';
               end if;
               END IF;
            when G20_3 =>
            WHEN s532 =>
               if (rdy_i = '1') then
               IF (rdy_i = '1') THEN
                  sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
                  sig_PC <= adr_sp_i;
                  reg_sel_pc_in <= '1';
               END IF;
                  reg_sel_pc_val <= "11";
            WHEN s533 =>
                  zw_b1 <= d_i;
               sig_PC <= adr_sp_i;
               end if;
            WHEN s534 =>
            when G20_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G21_1 =>
 
               if (rdy_i = '1') then
               sig_PC <= adr_sp_i;
               sig_PC <= adr_sp_i;
            WHEN s535 =>
                  zw_b1 <= d_i;
               IF (rdy_i = '1') THEN
               end if;
                  sig_PC <= X"FFFB";
            when G21_3 =>
 
               sig_PC <= adr_sp_i;
 
            when G21_4 =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '1';
 
               reg_sel_pc_val <= "11";
 
            when G21_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1 (7 downto 0);
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G22_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G22_e =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '0';
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            when G23_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G23_e =>
 
               sig_PC <= adr_pc_i;
 
               reg_sel_pc_in <= '0';
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            when G24_2 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G24_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G25_2 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G25_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F <= d_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G26_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G26_2 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G26_3 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
                  reg_F <= d_i;
                  reg_sel_pc_in <= '1';
                  reg_sel_pc_in <= '1';
 
 
                  reg_sel_pc_val <= "11";
                  reg_sel_pc_val <= "11";
 
               end if;
 
            when G26_4 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G26_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G27_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G27_2 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G27_3 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
                  zw_b1 <= d_i;
 
                  reg_sel_pc_in <= '1';
 
                  reg_sel_pc_val <= "00";
 
               end if;
 
            when G27_4 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
               end if;
 
            when G27_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G28_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G28_2 =>
 
               sig_PC <= adr_sp_i;
 
            when G28_3 =>
 
               sig_PC <= adr_sp_i;
 
            when G28_4 =>
 
               sig_PC <= X"FFFE";
 
            when G28_5 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= X"FFFF";
                  zw_b1 <= d_i;
                  zw_b1 <= d_i;
               END IF;
               end if;
            WHEN s536 =>
            when G28_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= d_i & zw_b1;
 
                  reg_F(2) <= '1';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G29_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_sp_i;
 
               end if;
 
            when G29_2 =>
 
               sig_PC <= adr_sp_i;
 
            when G29_3 =>
 
               sig_PC <= adr_sp_i;
 
            when G29_4 =>
               sig_PC <= X"FFFA";
               sig_PC <= X"FFFA";
            WHEN s537 =>
            when G29_5 =>
               IF (rdy_i = '1') THEN
               if (rdy_i = '1') then
 
                  sig_PC <= X"FFFB";
 
                  reg_sel_pc_in <= '1';
 
                  reg_sel_pc_val <= "11";
 
                  zw_b1 <= d_i;
 
               end if;
 
            when G29_e =>
 
               if (rdy_i = '1') then
                  sig_PC <= d_i & zw_b1;
                  sig_PC <= d_i & zw_b1;
                  reg_sel_pc_in <= '0';
                  reg_sel_pc_in <= '0';
 
 
                  reg_sel_pc_val <= "00";
                  reg_sel_pc_val <= "00";
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_in <= '0';
                  reg_sel_sp_as <= '1';
                  reg_sel_sp_as <= '1';
               END IF;
               end if;
            WHEN OTHERS =>
            when G2_1 =>
               NULL;
               if (rdy_i = '1') then
         END CASE;
                  sig_PC <= adr_pc_i;
      END IF;
                  reg_F(0) <= '1';
   END PROCESS clocked_proc;
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G30_1 =>
 
               sig_PC <= adr_sp_i;
 
            when G30_2 =>
 
               sig_PC <= adr_sp_i;
 
               reg_sel_pc_in <= '1';
 
               reg_sel_pc_val <= "00";
 
            when G30_3 =>
 
               sig_PC <= adr_sp_i;
 
               reg_sel_pc_in <= '0';
 
               reg_sel_pc_val <= "00";
 
            when G30_4 =>
 
               sig_PC <= adr_pc_i;
 
            when G30_5 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  zw_b1 <= d_i;
 
                  reg_sel_pc_in <= '1';
 
                  reg_sel_pc_val <= "11";
 
               end if;
 
            when G30_e =>
 
               if (rdy_i = '1') then
 
                  sig_PC  <= d_i & zw_b1;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G31_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(7);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G32_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(0);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G33_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(7);
 
                  reg_F(0) <= q_a_i(7);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G34_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= q_a_i(0);
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G3_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(3) <= '1';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G4_1 =>
 
               sig_PC <= adr_pc_i;
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(2) <= '1';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G5_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(0) <= '0';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G6_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(3) <= '0';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G7_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(2) <= '0';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G8_1 =>
 
               if (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(6) <= '0';
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when G9_1 =>
 
               if (rdy_i = '1' and
 
                   zw_REG_OP = X"9A") then
 
                  sig_PC <= adr_pc_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               elsif (rdy_i = '1' and
 
                      zw_REG_OP = X"BA") then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               elsif (rdy_i = '1') then
 
                  sig_PC <= adr_pc_i;
 
                  reg_F(7) <= reg_7flag_i;
 
                  reg_F(1) <= reg_1flag_i;
 
                  reg_sel_pc_in <= '0';
 
                  reg_sel_pc_val <= "00";
 
                  reg_sel_sp_in <= '0';
 
                  reg_sel_sp_as <= '1';
 
               end if;
 
            when RES =>
 
               reg_sel_pc_in <= '0';
 
               reg_sel_pc_val <= "00";
 
               sig_PC <= adr_nxt_pc_i;
 
               reg_sel_pc_in <= '0';
 
               reg_sel_pc_val <= "00";
 
               reg_sel_sp_in <= '0';
 
               reg_sel_sp_as <= '1';
 
            when others =>
 
               null;
 
         end case;
 
      end if;
 
   end process clocked_proc;
 
 
   -----------------------------------------------------------------
   -----------------------------------------------------------------
   nextstate_proc : PROCESS (
   nextstate_proc : process (
      adr_nxt_pc_i,
      adr_nxt_pc_i,
      current_state,
      current_state,
      d_i,
      d_i,
      irq_n_i,
      irq_n_i,
      nmi_i,
      nmi_i,
Line 2078... Line 1955...
      zw_REG_OP,
      zw_REG_OP,
      zw_b2,
      zw_b2,
      zw_b3
      zw_b3
   )
   )
   -----------------------------------------------------------------
   -----------------------------------------------------------------
   BEGIN
   begin
      CASE current_state IS
      case current_state is
         WHEN FETCH =>
         when FETCH =>
            IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
            if ((nmi_i = '1') and (rdy_i = '1')) then
               next_state <= s532;
               next_state <= G29_1;
            ELSIF ((irq_n_i = '0' and
            elsif ((irq_n_i = '0' and
                   reg_F(2) = '0') AND (rdy_i = '1')) THEN
                   reg_F(2) = '0') and (rdy_i = '1')) then
               next_state <= s548;
               next_state <= G28_1;
            ELSIF ((d_i = X"69" or
            elsif ((d_i = X"69" or
                   d_i = X"65" or
                   d_i = X"65" or
                   d_i = X"75" or
                   d_i = X"75" or
                   d_i = X"6D" or
                   d_i = X"6D" or
                   d_i = X"7D" or
                   d_i = X"7D" or
                   d_i = X"79" or
                   d_i = X"79" or
                   d_i = X"61" or
                   d_i = X"61" or
                   d_i = X"71") AND (rdy_i = '1')) THEN
                   d_i = X"71") and (rdy_i = '1')) then
               next_state <= s510;
               next_state <= G10_1;
            ELSIF ((d_i = X"06" or
            elsif ((d_i = X"06" or
                   d_i = X"16" or
                   d_i = X"16" or
                   d_i = X"0E" or
                   d_i = X"0E" or
                   d_i = X"1E") AND (rdy_i = '1')) THEN
                   d_i = X"1E") and (rdy_i = '1')) then
               next_state <= s403;
               next_state <= G11_1;
            ELSIF ((d_i = X"90" or
            elsif ((d_i = X"90" or
                   d_i = X"B0" or
                   d_i = X"B0" or
                   d_i = X"F0" or
                   d_i = X"F0" or
                   d_i = X"30" or
                   d_i = X"30" or
                   d_i = X"D0" or
                   d_i = X"D0" or
                   d_i = X"10" or
                   d_i = X"10" or
                   d_i = X"50" or
                   d_i = X"50" or
                   d_i = X"70") AND (rdy_i = '1')) THEN
                   d_i = X"70") and (rdy_i = '1')) then
               next_state <= s266;
               next_state <= G12_1;
            ELSIF ((d_i = X"24" or
            elsif ((d_i = X"24" or
                   d_i = X"2C") AND (rdy_i = '1')) THEN
                   d_i = X"2C") and (rdy_i = '1')) then
               next_state <= s351;
               next_state <= G13_1;
            ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"00") and (rdy_i = '1')) then
               next_state <= s526;
               next_state <= G18_1;
            ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"18") and (rdy_i = '1')) then
               next_state <= s12;
               next_state <= G5_1;
            ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"D8") and (rdy_i = '1')) then
               next_state <= s16;
               next_state <= G6_1;
            ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"58") and (rdy_i = '1')) then
               next_state <= s17;
               next_state <= G7_1;
            ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"B8") and (rdy_i = '1')) then
               next_state <= s24;
               next_state <= G8_1;
            ELSIF ((d_i = X"E0" or
            elsif ((d_i = X"E0" or
                   d_i = X"E4" or
                   d_i = X"E4" or
                   d_i = X"EC") AND (rdy_i = '1')) THEN
                   d_i = X"EC") and (rdy_i = '1')) then
               next_state <= s201;
               next_state <= G15_1;
            ELSIF ((d_i = X"C0" or
            elsif ((d_i = X"C0" or
                   d_i = X"C4" or
                   d_i = X"C4" or
                   d_i = X"CC") AND (rdy_i = '1')) THEN
                   d_i = X"CC") and (rdy_i = '1')) then
               next_state <= s201;
               next_state <= G15_1;
            ELSIF ((d_i = X"C6" or
            elsif ((d_i = X"C6" or
                   d_i = X"D6" or
                   d_i = X"D6" or
                   d_i = X"CE" or
                   d_i = X"CE" or
                   d_i = X"DE") AND (rdy_i = '1')) THEN
                   d_i = X"DE") and (rdy_i = '1')) then
               next_state <= s226;
               next_state <= G14_1;
            ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"CA") and (rdy_i = '1')) then
               next_state <= s25;
               next_state <= G19_1;
            ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"88") and (rdy_i = '1')) then
               next_state <= s25;
               next_state <= G19_1;
            ELSIF ((d_i = X"49" or
            elsif ((d_i = X"49" or
                   d_i = X"45" or
                   d_i = X"45" or
                   d_i = X"55" or
                   d_i = X"55" or
                   d_i = X"4D" or
                   d_i = X"4D" or
                   d_i = X"5D" or
                   d_i = X"5D" or
                   d_i = X"59" or
                   d_i = X"59" or
Line 2170... Line 2047...
                   d_i = X"D5" or
                   d_i = X"D5" or
                   d_i = X"CD" or
                   d_i = X"CD" or
                   d_i = X"DD" or
                   d_i = X"DD" or
                   d_i = X"D9" or
                   d_i = X"D9" or
                   d_i = X"C1" or
                   d_i = X"C1" or
                   d_i = X"D1") AND (rdy_i = '1')) THEN
                   d_i = X"D1") and (rdy_i = '1')) then
               next_state <= s201;
               next_state <= G15_1;
            ELSIF ((d_i = X"E6" or
            elsif ((d_i = X"E6" or
                   d_i = X"F6" or
                   d_i = X"F6" or
                   d_i = X"EE" or
                   d_i = X"EE" or
                   d_i = X"FE") AND (rdy_i = '1')) THEN
                   d_i = X"FE") and (rdy_i = '1')) then
               next_state <= s226;
               next_state <= G14_1;
            ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"E8") and (rdy_i = '1')) then
               next_state <= s25;
               next_state <= G19_1;
            ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"C8") and (rdy_i = '1')) then
               next_state <= s25;
               next_state <= G19_1;
            ELSIF ((d_i = X"4C" or
            elsif ((d_i = X"4C" or
                   d_i = X"6C") AND (rdy_i = '1')) THEN
                   d_i = X"6C") and (rdy_i = '1')) then
               next_state <= s271;
               next_state <= G20_1;
            ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"20") and (rdy_i = '1')) then
               next_state <= s397;
               next_state <= G21_1;
            ELSIF ((d_i = X"A9" or
            elsif ((d_i = X"A9" or
                   d_i = X"A5" or
                   d_i = X"A5" or
                   d_i = X"B5" or
                   d_i = X"B5" or
                   d_i = X"AD" or
                   d_i = X"AD" or
                   d_i = X"BD" or
                   d_i = X"BD" or
                   d_i = X"B9" or
                   d_i = X"B9" or
                   d_i = X"A1" or
                   d_i = X"A1" or
                   d_i = X"B1") AND (rdy_i = '1')) THEN
                   d_i = X"B1") and (rdy_i = '1')) then
               next_state <= s201;
               next_state <= G15_1;
            ELSIF ((d_i = X"A2" or
            elsif ((d_i = X"A2" or
                   d_i = X"A6" or
                   d_i = X"A6" or
                   d_i = X"B6" or
                   d_i = X"B6" or
                   d_i = X"AE" or
                   d_i = X"AE" or
                   d_i = X"BE") AND (rdy_i = '1')) THEN
                   d_i = X"BE") and (rdy_i = '1')) then
               next_state <= s201;
               next_state <= G15_1;
            ELSIF ((d_i = X"A0" or
            elsif ((d_i = X"A0" or
                   d_i = X"A4" or
                   d_i = X"A4" or
                   d_i = X"B4" or
                   d_i = X"B4" or
                   d_i = X"AC" or
                   d_i = X"AC" or
                   d_i = X"BC") AND (rdy_i = '1')) THEN
                   d_i = X"BC") and (rdy_i = '1')) then
               next_state <= s201;
               next_state <= G15_1;
            ELSIF ((d_i = X"46" or
            elsif ((d_i = X"46" or
                   d_i = X"56" or
                   d_i = X"56" or
                   d_i = X"4E" or
                   d_i = X"4E" or
                   d_i = X"5E") AND (rdy_i = '1')) THEN
                   d_i = X"5E") and (rdy_i = '1')) then
               next_state <= s403;
               next_state <= G11_1;
            ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"EA") and (rdy_i = '1')) then
               next_state <= s1;
               next_state <= G1_1;
            ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"48") and (rdy_i = '1')) then
               next_state <= s377;
               next_state <= G22_1;
            ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"08") and (rdy_i = '1')) then
               next_state <= s378;
               next_state <= G23_1;
            ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"68") and (rdy_i = '1')) then
               next_state <= s379;
               next_state <= G24_1;
            ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"28") and (rdy_i = '1')) then
               next_state <= s380;
               next_state <= G25_1;
            ELSIF ((d_i = X"26" or
            elsif ((d_i = X"26" or
                   d_i = X"36" or
                   d_i = X"36" or
                   d_i = X"2E" or
                   d_i = X"2E" or
                   d_i = X"3E") AND (rdy_i = '1')) THEN
                   d_i = X"3E") and (rdy_i = '1')) then
               next_state <= s403;
               next_state <= G11_1;
            ELSIF ((d_i = X"66" or
            elsif ((d_i = X"66" or
                   d_i = X"76" or
                   d_i = X"76" or
                   d_i = X"6E" or
                   d_i = X"6E" or
                   d_i = X"7E") AND (rdy_i = '1')) THEN
                   d_i = X"7E") and (rdy_i = '1')) then
               next_state <= s403;
               next_state <= G11_1;
            ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"40") and (rdy_i = '1')) then
               next_state <= s387;
               next_state <= G26_1;
            ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"60") and (rdy_i = '1')) then
               next_state <= s390;
               next_state <= G27_1;
            ELSIF ((d_i = X"E9" or
            elsif ((d_i = X"E9" or
                   d_i = X"E5" or
                   d_i = X"E5" or
                   d_i = X"F5" or
                   d_i = X"F5" or
                   d_i = X"ED" or
                   d_i = X"ED" or
                   d_i = X"FD" or
                   d_i = X"FD" or
                   d_i = X"F9" or
                   d_i = X"F9" or
                   d_i = X"E1" or
                   d_i = X"E1" or
                   d_i = X"F1") AND (rdy_i = '1')) THEN
                   d_i = X"F1") and (rdy_i = '1')) then
               next_state <= s511;
               next_state <= G16_1;
            ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"38") and (rdy_i = '1')) then
               next_state <= s2;
               next_state <= G2_1;
            ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"F8") and (rdy_i = '1')) then
               next_state <= s5;
               next_state <= G3_1;
            ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"78") and (rdy_i = '1')) then
               next_state <= s3;
               next_state <= G4_1;
            ELSIF ((d_i = X"85" or
            elsif ((d_i = X"85" or
                   d_i = X"95" or
                   d_i = X"95" or
                   d_i = X"8D" or
                   d_i = X"8D" or
                   d_i = X"9D" or
                   d_i = X"9D" or
                   d_i = X"99" or
                   d_i = X"99" or
                   d_i = X"81" or
                   d_i = X"81" or
                   d_i = X"91") AND (rdy_i = '1')) THEN
                   d_i = X"91") and (rdy_i = '1')) then
               next_state <= s177;
               next_state <= G17_1;
            ELSIF ((d_i = X"86" or
            elsif ((d_i = X"86" or
                   d_i = X"96" or
                   d_i = X"96" or
                   d_i = X"8E") AND (rdy_i = '1')) THEN
                   d_i = X"8E") and (rdy_i = '1')) then
               next_state <= s177;
               next_state <= G17_1;
            ELSIF ((d_i = X"84" or
            elsif ((d_i = X"84" or
                   d_i = X"94" or
                   d_i = X"94" or
                   d_i = X"8C") AND (rdy_i = '1')) THEN
                   d_i = X"8C") and (rdy_i = '1')) then
               next_state <= s177;
               next_state <= G17_1;
            ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"AA") and (rdy_i = '1')) then
               next_state <= s4;
               next_state <= G9_1;
            ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"0A") and (rdy_i = '1')) then
               next_state <= s404;
               next_state <= G31_1;
            ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"4A") and (rdy_i = '1')) then
               next_state <= s556;
               next_state <= G32_1;
            ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"2A") and (rdy_i = '1')) then
               next_state <= s557;
               next_state <= G33_1;
            ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"6A") and (rdy_i = '1')) then
               next_state <= s579;
               next_state <= G34_1;
            ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"A8") and (rdy_i = '1')) then
               next_state <= s4;
               next_state <= G9_1;
            ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"98") and (rdy_i = '1')) then
               next_state <= s4;
               next_state <= G9_1;
            ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"BA") and (rdy_i = '1')) then
               next_state <= s4;
               next_state <= G9_1;
            ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"8A") and (rdy_i = '1')) then
               next_state <= s4;
               next_state <= G9_1;
            ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"9A") and (rdy_i = '1')) then
               next_state <= s4;
               next_state <= G9_1;
            ELSIF (rdy_i = '1') THEN
            elsif (rdy_i = '1') then
               next_state <= s1;
               next_state <= G1_1;
            ELSE
            else
               next_state <= FETCH;
               next_state <= FETCH;
            END IF;
            end if;
         WHEN s1 =>
         when G10_1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' and
               next_state <= FETCH;
                zw_REG_OP = X"65") then
            ELSE
               next_state <= G10_e2;
               next_state <= s1;
            elsif (rdy_i = '1' and
            END IF;
                   zw_REG_OP = X"69" and
         WHEN s2 =>
                   reg_F(3) = '0') then
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s2;
 
            END IF;
 
         WHEN s5 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s5;
 
            END IF;
 
         WHEN s3 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s3;
 
            END IF;
 
         WHEN s4 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"9A") THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"BA") THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s4;
 
            END IF;
 
         WHEN s12 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s12;
 
            END IF;
 
         WHEN s16 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s16;
 
            END IF;
 
         WHEN s17 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s17;
 
            END IF;
 
         WHEN s24 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s24;
 
            END IF;
 
         WHEN s25 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s25;
 
            END IF;
 
         WHEN s271 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"4C") THEN
 
               next_state <= s307;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"6C") THEN
 
               next_state <= s273;
 
            ELSE
 
               next_state <= s271;
 
            END IF;
 
         WHEN s273 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s304;
 
            ELSE
 
               next_state <= s273;
 
            END IF;
 
         WHEN s304 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s307;
 
            ELSE
 
               next_state <= s304;
 
            END IF;
 
         WHEN s307 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s307;
 
            END IF;
 
         WHEN s177 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"85" OR
 
                zw_REG_OP = X"86" OR
 
                zw_REG_OP = X"84")) THEN
 
               next_state <= s184;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"95" OR
 
                   zw_REG_OP = X"94")) THEN
 
               next_state <= s185;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"8D" OR
 
                   zw_REG_OP = X"8E" OR
 
                   zw_REG_OP = X"8C")) THEN
 
               next_state <= s183;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"9D") THEN
 
               next_state <= s182;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"99") THEN
 
               next_state <= s180;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"91") THEN
 
               next_state <= s181;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"81") THEN
 
               next_state <= s186;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"96") THEN
 
               next_state <= s185;
 
            ELSE
 
               next_state <= s177;
 
            END IF;
 
         WHEN s180 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s191;
 
            ELSE
 
               next_state <= s180;
 
            END IF;
 
         WHEN s181 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s189;
 
            ELSE
 
               next_state <= s181;
 
            END IF;
 
         WHEN s182 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s191;
 
            ELSE
 
               next_state <= s182;
 
            END IF;
 
         WHEN s183 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s187;
 
            ELSE
 
               next_state <= s183;
 
            END IF;
 
         WHEN s184 =>
 
            next_state <= FETCH;
 
         WHEN s185 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s190;
 
            ELSE
 
               next_state <= s185;
 
            END IF;
 
         WHEN s186 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s188;
 
            ELSE
 
               next_state <= s186;
 
            END IF;
 
         WHEN s187 =>
 
            next_state <= FETCH;
 
         WHEN s188 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s192;
 
            ELSE
 
               next_state <= s188;
 
            END IF;
 
         WHEN s189 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s191;
 
            ELSE
 
               next_state <= s189;
 
            END IF;
 
         WHEN s190 =>
 
            next_state <= FETCH;
 
         WHEN s191 =>
 
            next_state <= s193;
 
         WHEN s192 =>
 
            next_state <= s193;
 
         WHEN s193 =>
 
            next_state <= FETCH;
 
         WHEN s377 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s381;
 
            ELSE
 
               next_state <= s377;
 
            END IF;
 
         WHEN s381 =>
 
            next_state <= FETCH;
 
         WHEN s378 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s382;
 
            ELSE
 
               next_state <= s378;
 
            END IF;
 
         WHEN s382 =>
 
            next_state <= FETCH;
 
         WHEN s379 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s383;
 
            ELSE
 
               next_state <= s379;
 
            END IF;
 
         WHEN s383 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s384;
 
            ELSE
 
               next_state <= s383;
 
            END IF;
 
         WHEN s384 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s384;
 
            END IF;
 
         WHEN s380 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s385;
 
            ELSE
 
               next_state <= s380;
 
            END IF;
 
         WHEN s385 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s386;
 
            ELSE
 
               next_state <= s385;
 
            END IF;
 
         WHEN s386 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s386;
 
            END IF;
 
         WHEN s387 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s388;
 
            ELSE
 
               next_state <= s387;
 
            END IF;
 
         WHEN s388 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s389;
 
            ELSE
 
               next_state <= s388;
 
            END IF;
 
         WHEN s389 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s391;
 
            ELSE
 
               next_state <= s389;
 
            END IF;
 
         WHEN s391 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s392;
 
            ELSE
 
               next_state <= s391;
 
            END IF;
 
         WHEN s392 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s392;
 
            END IF;
 
         WHEN s390 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s393;
 
            ELSE
 
               next_state <= s390;
 
            END IF;
 
         WHEN s393 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s394;
 
            ELSE
 
               next_state <= s393;
 
            END IF;
 
         WHEN s394 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s395;
 
            ELSE
 
               next_state <= s394;
 
            END IF;
 
         WHEN s395 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s396;
 
            ELSE
 
               next_state <= s395;
 
            END IF;
 
         WHEN s396 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s396;
 
            END IF;
 
         WHEN s397 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s398;
 
            ELSE
 
               next_state <= s397;
 
            END IF;
 
         WHEN s398 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s399;
 
            ELSE
 
               next_state <= s398;
 
            END IF;
 
         WHEN s399 =>
 
            next_state <= s400;
 
         WHEN s400 =>
 
            next_state <= s401;
 
         WHEN s401 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s401;
 
            END IF;
 
         WHEN s526 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s527;
 
            ELSE
 
               next_state <= s526;
 
            END IF;
 
         WHEN s527 =>
 
            next_state <= s528;
 
         WHEN s528 =>
 
            next_state <= s529;
 
         WHEN s529 =>
 
            next_state <= s531;
 
         WHEN s530 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s530;
 
            END IF;
 
         WHEN s531 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s530;
 
            ELSE
 
               next_state <= s531;
 
            END IF;
 
         WHEN s544 =>
 
            next_state <= s550;
 
         WHEN s545 =>
 
            next_state <= s546;
 
         WHEN s546 =>
 
            next_state <= s547;
 
         WHEN s547 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s549;
 
            ELSE
 
               next_state <= s547;
 
            END IF;
 
         WHEN s549 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s549;
 
            END IF;
 
         WHEN s550 =>
 
            next_state <= s545;
 
         WHEN s404 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s404;
 
            END IF;
 
         WHEN s556 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s556;
 
            END IF;
 
         WHEN s557 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s557;
 
            END IF;
 
         WHEN s579 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s579;
 
            END IF;
 
         WHEN s201 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
 
                zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
 
                zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
 
                zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
 
               next_state <= s224;
 
            ELSIF ((rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
 
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
 
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
 
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
 
               next_state <= FETCH;
 
            ELSIF ((rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
 
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
 
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
 
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
 
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_REG_OP = X"75") then
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
               next_state <= G10_2;
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                   zw_REG_OP = X"6D") then
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
               next_state <= G10_3;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"7D") then
 
               next_state <= G10_4;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"79") then
 
               next_state <= G10_4;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"71") then
 
               next_state <= G10_5;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"61") then
 
               next_state <= G10_7;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"69" and
 
                   reg_F(3) = '1') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1' and
            else
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
               next_state <= G10_1;
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
            end if;
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
         when G10_2 =>
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
            if (rdy_i = '1') then
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
               next_state <= G10_e2;
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
            else
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
               next_state <= G10_2;
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
            end if;
 
         when G10_3 =>
 
            if (rdy_i = '1') then
 
               next_state <= G10_e2;
 
            else
 
               next_state <= G10_3;
 
            end if;
 
         when G10_4 =>
 
            if (rdy_i = '1') then
 
               next_state <= G10_e1;
 
            else
 
               next_state <= G10_4;
 
            end if;
 
         when G10_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G10_6;
 
            else
 
               next_state <= G10_5;
 
            end if;
 
         when G10_6 =>
 
            if (rdy_i = '1') then
 
               next_state <= G10_e1;
 
            else
 
               next_state <= G10_6;
 
            end if;
 
         when G10_7 =>
 
            if (rdy_i = '1') then
 
               next_state <= G10_e3;
 
            else
 
               next_state <= G10_7;
 
            end if;
 
         when G10_e1 =>
 
            if (rdy_i = '1' AND
 
                zw_b2(0) = '0' and
 
                reg_F(3) = '0') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' AND
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_b2(0) = '0' and
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
                   reg_F(3) = '1') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1') then
                   (zw_REG_OP = X"B5" OR
               next_state <= G10_e2;
                   zw_REG_OP = X"B4" OR
            else
                   zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
               next_state <= G10_e1;
                   zw_REG_OP = X"35" OR
            end if;
                   zw_REG_OP = X"D5")) THEN
         when G10_e2 =>
               next_state <= s217;
            if (rdy_i = '1' and
            ELSIF (rdy_i = '1' and
                reg_F(3) = '0') then
                   (zw_REG_OP = X"AD" OR
               next_state <= FETCH;
                   zw_REG_OP = X"AE" OR
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"AC" OR
                   reg_F(3) = '1') then
                   zw_REG_OP = X"4D" OR
               next_state <= FETCH;
                   zw_REG_OP = X"0D" OR
            else
                   zw_REG_OP = X"2D" OR
               next_state <= G10_e2;
                   zw_REG_OP = X"CD" OR
            end if;
                   zw_REG_OP = X"EC" OR
         when G10_e3 =>
                   zw_REG_OP = X"CC")) THEN
            if (rdy_i = '1') then
               next_state <= s202;
               next_state <= G10_3;
            ELSIF (rdy_i = '1' and
            else
                   (zw_REG_OP = X"BD" OR
               next_state <= G10_e3;
                   zw_REG_OP = X"BC" OR
            end if;
                   zw_REG_OP = X"5D" OR
         when G11_1 =>
                   zw_REG_OP = X"1D" OR
            if (rdy_i = '1' and
                   zw_REG_OP = X"3D" OR
                (zw_REG_OP = X"1E" or
                   zw_REG_OP = X"DD")) THEN
                zw_REG_OP = X"7E" or
               next_state <= s210;
                zw_REG_OP = X"3E" or
            ELSIF (rdy_i = '1' and
                zw_REG_OP = X"5E")) then
 
               next_state <= G11_6;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"06" or
 
                   zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"46")) then
 
               next_state <= G11_3;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"16" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"56")) then
 
               next_state <= G11_2;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"0E" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"4E")) then
 
               next_state <= G11_5;
 
            else
 
               next_state <= G11_1;
 
            end if;
 
         when G11_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G11_3;
 
            else
 
               next_state <= G11_2;
 
            end if;
 
         when G11_3 =>
 
            if (rdy_i = '1') then
 
               next_state <= G11_4;
 
            else
 
               next_state <= G11_3;
 
            end if;
 
         when G11_4 =>
 
            if (rdy_i = '1' and
 
                (zw_REG_OP = X"06" or
 
                zw_REG_OP = X"16" or
 
                zw_REG_OP = X"0E" or
 
                zw_REG_OP = X"1E")) then
 
               next_state <= G11_e;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"46" or
 
                   zw_REG_OP = X"56" or
 
                   zw_REG_OP = X"4E" or
 
                   zw_REG_OP = X"5E")) then
 
               next_state <= G11_e;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"3E")) then
 
               next_state <= G11_e;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"7E")) then
 
               next_state <= G11_e;
 
            else
 
               next_state <= G11_4;
 
            end if;
 
         when G11_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G11_3;
 
            else
 
               next_state <= G11_5;
 
            end if;
 
         when G11_6 =>
 
            if (rdy_i = '1') then
 
               next_state <= G11_7;
 
            else
 
               next_state <= G11_6;
 
            end if;
 
         when G11_7 =>
 
            if (rdy_i = '1') then
 
               next_state <= G11_3;
 
            else
 
               next_state <= G11_7;
 
            end if;
 
         when G11_e =>
 
            next_state <= FETCH;
 
         when G12_1 =>
 
            if (rdy_i = '1' and (
 
                (reg_F(0) = '1' and zw_REG_OP = X"90") or
 
                (reg_F(0) = '0' and zw_REG_OP = X"B0") or
 
                (reg_F(1) = '0' and zw_REG_OP = X"F0") or
 
                (reg_F(7) = '0' and zw_REG_OP = X"30") or
 
                (reg_F(1) = '1' and zw_REG_OP = X"D0") or
 
                (reg_F(7) = '1' and zw_REG_OP = X"10") or
 
                (reg_F(6) = '1' and zw_REG_OP = X"50") or
 
                (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
 
               next_state <= FETCH;
 
            elsif (rdy_i = '1') then
 
               next_state <= G12_e1;
 
            else
 
               next_state <= G12_1;
 
            end if;
 
         when G12_e1 =>
 
            if (rdy_i = '1' and
 
                zw_b3 = adr_nxt_pc_i (15 downto 8)) then
 
               next_state <= FETCH;
 
            elsif (rdy_i = '1') then
 
               next_state <= G12_e2;
 
            else
 
               next_state <= G12_e1;
 
            end if;
 
         when G12_e2 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G12_e2;
 
            end if;
 
         when G13_1 =>
 
            if (rdy_i = '1' and
 
                zw_REG_OP = X"24") then
 
               next_state <= G13_e;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"2C") then
 
               next_state <= G13_2;
 
            else
 
               next_state <= G13_1;
 
            end if;
 
         when G13_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G13_e;
 
            else
 
               next_state <= G13_2;
 
            end if;
 
         when G13_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G13_e;
 
            end if;
 
         when G14_1 =>
 
            if (rdy_i = '1' and
 
                (zw_REG_OP = X"C6" OR
 
                zw_REG_OP = X"E6")) then
 
               next_state <= G14_3;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"D6" OR
 
                   zw_REG_OP = X"F6")) then
 
               next_state <= G14_2;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"CE" OR
 
                   zw_REG_OP = X"EE")) then
 
               next_state <= G14_5;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"DE" OR
 
                   zw_REG_OP = X"FE")) then
 
               next_state <= G14_6;
 
            else
 
               next_state <= G14_1;
 
            end if;
 
         when G14_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G14_3;
 
            else
 
               next_state <= G14_2;
 
            end if;
 
         when G14_3 =>
 
            if (rdy_i = '1') then
 
               next_state <= G14_4;
 
            else
 
               next_state <= G14_3;
 
            end if;
 
         when G14_4 =>
 
            if (rdy_i = '1') then
 
               next_state <= G14_e;
 
            else
 
               next_state <= G14_4;
 
            end if;
 
         when G14_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G14_3;
 
            else
 
               next_state <= G14_5;
 
            end if;
 
         when G14_6 =>
 
            if (rdy_i = '1') then
 
               next_state <= G14_7;
 
            else
 
               next_state <= G14_6;
 
            end if;
 
         when G14_7 =>
 
            if (rdy_i = '1') then
 
               next_state <= G14_3;
 
            else
 
               next_state <= G14_7;
 
            end if;
 
         when G14_e =>
 
            next_state <= FETCH;
 
         when G15_1 =>
 
            if (rdy_i = '1' and
 
                (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
 
                zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
 
                zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
 
                zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
 
               next_state <= G15_e2;
 
            elsif ((rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
 
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
 
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
 
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
 
               next_state <= FETCH;
 
            elsif ((rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
 
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
 
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
 
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
 
               next_state <= FETCH;
 
            elsif ((rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
 
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
 
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
 
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
 
               next_state <= FETCH;
 
            elsif ((rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
 
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
 
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
 
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
 
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
 
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
 
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
 
               next_state <= FETCH;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
 
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
 
               next_state <= FETCH;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"B5" OR
 
                   zw_REG_OP = X"B4" OR
 
                   zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
 
                   zw_REG_OP = X"35" OR
 
                   zw_REG_OP = X"D5")) then
 
               next_state <= G15_2;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"AD" OR
 
                   zw_REG_OP = X"AE" OR
 
                   zw_REG_OP = X"AC" OR
 
                   zw_REG_OP = X"4D" OR
 
                   zw_REG_OP = X"0D" OR
 
                   zw_REG_OP = X"2D" OR
 
                   zw_REG_OP = X"CD" OR
 
                   zw_REG_OP = X"EC" OR
 
                   zw_REG_OP = X"CC")) then
 
               next_state <= G15_3;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"BD" OR
 
                   zw_REG_OP = X"BC" OR
 
                   zw_REG_OP = X"5D" OR
 
                   zw_REG_OP = X"1D" OR
 
                   zw_REG_OP = X"3D" OR
 
                   zw_REG_OP = X"DD")) then
 
               next_state <= G15_4;
 
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"B9" OR
                   (zw_REG_OP = X"B9" OR
                   zw_REG_OP = X"BE" OR
                   zw_REG_OP = X"BE" OR
                   zw_REG_OP = X"59" OR
                   zw_REG_OP = X"59" OR
                   zw_REG_OP = X"19" OR
                   zw_REG_OP = X"19" OR
                   zw_REG_OP = X"39" OR
                   zw_REG_OP = X"39" OR
                   zw_REG_OP = X"D9")) THEN
                   zw_REG_OP = X"D9")) then
               next_state <= s211;
               next_state <= G15_4;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"B1" OR
                   (zw_REG_OP = X"B1" OR
                   zw_REG_OP = X"51" OR
                   zw_REG_OP = X"51" OR
                   zw_REG_OP = X"11" OR
                   zw_REG_OP = X"11" OR
                   zw_REG_OP = X"31" OR
                   zw_REG_OP = X"31" OR
                   zw_REG_OP = X"D1")) THEN
                   zw_REG_OP = X"D1")) then
               next_state <= s215;
               next_state <= G15_5;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"A1" OR
                   (zw_REG_OP = X"A1" OR
                   zw_REG_OP = X"41" OR
                   zw_REG_OP = X"41" OR
                   zw_REG_OP = X"01" OR
                   zw_REG_OP = X"01" OR
                   zw_REG_OP = X"21" OR
                   zw_REG_OP = X"21" OR
                   zw_REG_OP = X"C1")) THEN
                   zw_REG_OP = X"C1")) then
               next_state <= s218;
               next_state <= G15_7;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"B6") THEN
                   zw_REG_OP = X"B6") then
               next_state <= s217;
               next_state <= G15_2;
            ELSE
            else
               next_state <= s201;
               next_state <= G15_1;
            END IF;
            end if;
         WHEN s202 =>
         when G15_2 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s224;
               next_state <= G15_e2;
            ELSE
            else
               next_state <= s202;
               next_state <= G15_2;
            END IF;
            end if;
         WHEN s210 =>
         when G15_3 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s225;
               next_state <= G15_e2;
            ELSE
            else
               next_state <= s210;
               next_state <= G15_3;
            END IF;
            end if;
         WHEN s211 =>
         when G15_4 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s225;
               next_state <= G15_e1;
            ELSE
            else
               next_state <= s211;
               next_state <= G15_4;
            END IF;
            end if;
         WHEN s215 =>
         when G15_5 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s223;
               next_state <= G15_6;
            ELSE
            else
               next_state <= s215;
               next_state <= G15_5;
            END IF;
            end if;
         WHEN s217 =>
         when G15_6 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s224;
               next_state <= G15_e1;
            ELSE
            else
               next_state <= s217;
               next_state <= G15_6;
            END IF;
            end if;
         WHEN s218 =>
         when G15_7 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s222;
               next_state <= G15_e3;
            ELSE
            else
               next_state <= s218;
               next_state <= G15_7;
            END IF;
            end if;
         WHEN s222 =>
         when G15_e1 =>
            IF (rdy_i = '1') THEN
            if ((rdy_i = '1' AND
               next_state <= s202;
                zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
            ELSE
 
               next_state <= s222;
 
            END IF;
 
         WHEN s223 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s225;
 
            ELSE
 
               next_state <= s223;
 
            END IF;
 
         WHEN s224 =>
 
            IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
 
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
            elsif ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
            elsif ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
            elsif ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1') THEN
            elsif (rdy_i = '1' AND
 
                   zw_b2(0) = '0') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSE
            elsif (rdy_i = '1') then
               next_state <= s224;
               next_state <= G15_e2;
            END IF;
            else
         WHEN s225 =>
               next_state <= G15_e1;
            IF ((rdy_i = '1' AND
            end if;
                zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
         when G15_e2 =>
 
            if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1' AND
            elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                   zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
 
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1' AND
            elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                   zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
 
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF ((rdy_i = '1' AND
            elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                   zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
 
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1' AND
            elsif (rdy_i = '1') then
                   zw_b2(0) = '0') THEN
 
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1') THEN
            else
               next_state <= s224;
               next_state <= G15_e2;
            ELSE
            end if;
               next_state <= s225;
         when G15_e3 =>
            END IF;
            if (rdy_i = '1') then
         WHEN s226 =>
               next_state <= G15_3;
            IF (rdy_i = '1' and
            else
                (zw_REG_OP = X"C6" OR
               next_state <= G15_e3;
                zw_REG_OP = X"E6")) THEN
            end if;
               next_state <= s343;
         when G16_1 =>
            ELSIF (rdy_i = '1' and
            if (rdy_i = '1' and
                   (zw_REG_OP = X"D6" OR
                zw_REG_OP = X"E5") then
                   zw_REG_OP = X"F6")) THEN
               next_state <= G16_e2;
               next_state <= s247;
            elsif (rdy_i = '1' and
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"CE" OR
 
                   zw_REG_OP = X"EE")) THEN
 
               next_state <= s243;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"DE" OR
 
                   zw_REG_OP = X"FE")) THEN
 
               next_state <= s244;
 
            ELSE
 
               next_state <= s226;
 
            END IF;
 
         WHEN s243 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s343;
 
            ELSE
 
               next_state <= s243;
 
            END IF;
 
         WHEN s244 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s344;
 
            ELSE
 
               next_state <= s244;
 
            END IF;
 
         WHEN s247 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s343;
 
            ELSE
 
               next_state <= s247;
 
            END IF;
 
         WHEN s344 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s343;
 
            ELSE
 
               next_state <= s344;
 
            END IF;
 
         WHEN s343 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s250;
 
            ELSE
 
               next_state <= s343;
 
            END IF;
 
         WHEN s250 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s251;
 
            ELSE
 
               next_state <= s250;
 
            END IF;
 
         WHEN s251 =>
 
            next_state <= FETCH;
 
         WHEN s351 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"24") THEN
 
               next_state <= s361;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"2C") THEN
 
               next_state <= s360;
 
            ELSE
 
               next_state <= s351;
 
            END IF;
 
         WHEN s361 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s361;
 
            END IF;
 
         WHEN s360 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s361;
 
            ELSE
 
               next_state <= s360;
 
            END IF;
 
         WHEN s403 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"1E" or
 
                zw_REG_OP = X"7E" or
 
                zw_REG_OP = X"3E" or
 
                zw_REG_OP = X"5E")) THEN
 
               next_state <= s407;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"06" or
 
                   zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"46")) THEN
 
               next_state <= s413;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"16" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"56")) THEN
 
               next_state <= s409;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"0E" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"4E")) THEN
 
               next_state <= s406;
 
            ELSE
 
               next_state <= s403;
 
            END IF;
 
         WHEN s406 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s413;
 
            ELSE
 
               next_state <= s406;
 
            END IF;
 
         WHEN s407 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s412;
 
            ELSE
 
               next_state <= s407;
 
            END IF;
 
         WHEN s409 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s413;
 
            ELSE
 
               next_state <= s409;
 
            END IF;
 
         WHEN s412 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s413;
 
            ELSE
 
               next_state <= s412;
 
            END IF;
 
         WHEN s413 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s416;
 
            ELSE
 
               next_state <= s413;
 
            END IF;
 
         WHEN s416 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"06" or
 
                zw_REG_OP = X"16" or
 
                zw_REG_OP = X"0E" or
 
                zw_REG_OP = X"1E")) THEN
 
               next_state <= s418;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"46" or
 
                   zw_REG_OP = X"56" or
 
                   zw_REG_OP = X"4E" or
 
                   zw_REG_OP = X"5E")) THEN
 
               next_state <= s418;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"3E")) THEN
 
               next_state <= s418;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"7E")) THEN
 
               next_state <= s418;
 
            ELSE
 
               next_state <= s416;
 
            END IF;
 
         WHEN s418 =>
 
            next_state <= FETCH;
 
         WHEN s510 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"65") THEN
 
               next_state <= s565;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"69" and
 
                   reg_F(3) = '0') THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"75") THEN
 
               next_state <= s560;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"6D") THEN
 
               next_state <= s553;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"7D") THEN
 
               next_state <= s555;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"79") THEN
 
               next_state <= s555;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"71") THEN
 
               next_state <= s558;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"61") THEN
 
               next_state <= s561;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"69" and
 
                   reg_F(3) = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s510;
 
            END IF;
 
         WHEN s553 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s565;
 
            ELSE
 
               next_state <= s553;
 
            END IF;
 
         WHEN s555 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s564;
 
            ELSE
 
               next_state <= s555;
 
            END IF;
 
         WHEN s558 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s566;
 
            ELSE
 
               next_state <= s558;
 
            END IF;
 
         WHEN s560 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s565;
 
            ELSE
 
               next_state <= s560;
 
            END IF;
 
         WHEN s561 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s563;
 
            ELSE
 
               next_state <= s561;
 
            END IF;
 
         WHEN s563 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s553;
 
            ELSE
 
               next_state <= s563;
 
            END IF;
 
         WHEN s564 =>
 
            IF (rdy_i = '1' AND
 
                zw_b2(0) = '0' and
 
                reg_F(3) = '0') THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1' AND
 
                   zw_b2(0) = '0' and
 
                   reg_F(3) = '1') THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1') THEN
 
               next_state <= s565;
 
            ELSE
 
               next_state <= s564;
 
            END IF;
 
         WHEN s565 =>
 
            IF (rdy_i = '1' and
 
                reg_F(3) = '0') THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1' and
 
                   reg_F(3) = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s565;
 
            END IF;
 
         WHEN s566 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s564;
 
            ELSE
 
               next_state <= s566;
 
            END IF;
 
         WHEN s266 =>
 
            IF (rdy_i = '1' and (
 
                (reg_F(0) = '1' and zw_REG_OP = X"90") or
 
                (reg_F(0) = '0' and zw_REG_OP = X"B0") or
 
                (reg_F(1) = '0' and zw_REG_OP = X"F0") or
 
                (reg_F(7) = '0' and zw_REG_OP = X"30") or
 
                (reg_F(1) = '1' and zw_REG_OP = X"D0") or
 
                (reg_F(7) = '1' and zw_REG_OP = X"10") or
 
                (reg_F(6) = '1' and zw_REG_OP = X"50") or
 
                (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1') THEN
 
               next_state <= s301;
 
            ELSE
 
               next_state <= s266;
 
            END IF;
 
         WHEN s301 =>
 
            IF (rdy_i = '1' and
 
                zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
 
               next_state <= FETCH;
 
            ELSIF (rdy_i = '1') THEN
 
               next_state <= s302;
 
            ELSE
 
               next_state <= s301;
 
            END IF;
 
         WHEN s302 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= FETCH;
 
            ELSE
 
               next_state <= s302;
 
            END IF;
 
         WHEN RES =>
 
            next_state <= s544;
 
         WHEN s511 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"E5") THEN
 
               next_state <= s574;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"E9" and
                   zw_REG_OP = X"E9" and
                   reg_F(3) = '0') THEN
                   reg_F(3) = '0') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"F5") THEN
                   zw_REG_OP = X"F5") then
               next_state <= s569;
               next_state <= G16_2;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"ED") THEN
                   zw_REG_OP = X"ED") then
               next_state <= s559;
               next_state <= G16_3;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"FD") THEN
                   zw_REG_OP = X"FD") then
               next_state <= s562;
               next_state <= G16_4;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"F9") THEN
                   zw_REG_OP = X"F9") then
               next_state <= s567;
               next_state <= G16_4;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"F1") THEN
                   zw_REG_OP = X"F1") then
               next_state <= s568;
               next_state <= G16_5;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"E1") THEN
                   zw_REG_OP = X"E1") then
               next_state <= s570;
               next_state <= G16_7;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"E9" and
                   zw_REG_OP = X"E9" and
                   reg_F(3) = '1') THEN
                   reg_F(3) = '1') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSE
            else
               next_state <= s511;
               next_state <= G16_1;
            END IF;
            end if;
         WHEN s559 =>
         when G16_2 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s574;
               next_state <= G16_e2;
            ELSE
            else
               next_state <= s559;
               next_state <= G16_2;
            END IF;
            end if;
         WHEN s562 =>
         when G16_3 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s573;
               next_state <= G16_e2;
            ELSE
            else
               next_state <= s562;
               next_state <= G16_3;
            END IF;
            end if;
         WHEN s567 =>
         when G16_4 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s573;
               next_state <= G16_e1;
            ELSE
            else
               next_state <= s567;
               next_state <= G16_4;
            END IF;
            end if;
         WHEN s568 =>
         when G16_5 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s571;
               next_state <= G16_6;
            ELSE
            else
               next_state <= s568;
               next_state <= G16_5;
            END IF;
            end if;
         WHEN s569 =>
         when G16_6 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s574;
               next_state <= G16_e1;
            ELSE
            else
               next_state <= s569;
               next_state <= G16_6;
            END IF;
            end if;
         WHEN s570 =>
         when G16_7 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s572;
               next_state <= G16_e3;
            ELSE
            else
               next_state <= s570;
               next_state <= G16_7;
            END IF;
            end if;
         WHEN s571 =>
         when G16_e1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' AND
               next_state <= s573;
 
            ELSE
 
               next_state <= s571;
 
            END IF;
 
         WHEN s572 =>
 
            IF (rdy_i = '1') THEN
 
               next_state <= s559;
 
            ELSE
 
               next_state <= s572;
 
            END IF;
 
         WHEN s573 =>
 
            IF (rdy_i = '1' AND
 
                zw_b2(0) = '0' and
                zw_b2(0) = '0' and
                reg_F(3) = '0') THEN
                reg_F(3) = '0') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1' AND
            elsif (rdy_i = '1' AND
                   zw_b2(0) = '0' and
                   zw_b2(0) = '0' and
                   reg_F(3) = '1') THEN
                   reg_F(3) = '1') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1') THEN
            elsif (rdy_i = '1') then
               next_state <= s574;
               next_state <= G16_e2;
            ELSE
            else
               next_state <= s573;
               next_state <= G16_e1;
            END IF;
            end if;
         WHEN s574 =>
         when G16_e2 =>
            IF (rdy_i = '1' and
            if (rdy_i = '1' and
                reg_F(3) = '0') THEN
                reg_F(3) = '0') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   reg_F(3) = '1') THEN
                   reg_F(3) = '1') then
               next_state <= FETCH;
               next_state <= FETCH;
            ELSE
            else
               next_state <= s574;
               next_state <= G16_e2;
            END IF;
            end if;
         WHEN s548 =>
         when G16_e3 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               next_state <= s551;
               next_state <= G16_3;
            ELSE
            else
               next_state <= s548;
               next_state <= G16_e3;
            END IF;
            end if;
         WHEN s551 =>
         when G17_1 =>
            next_state <= s552;
            if (rdy_i = '1' and
         WHEN s552 =>
                (zw_REG_OP = X"85" OR
            next_state <= s576;
                zw_REG_OP = X"86" OR
         WHEN s575 =>
                zw_REG_OP = X"84")) then
            IF (rdy_i = '1') THEN
               next_state <= G17_e;
               next_state <= s577;
            elsif (rdy_i = '1' and
            ELSE
                   (zw_REG_OP = X"95" OR
               next_state <= s575;
                   zw_REG_OP = X"94")) then
            END IF;
               next_state <= G17_2;
         WHEN s576 =>
            elsif (rdy_i = '1' and
            next_state <= s575;
                   (zw_REG_OP = X"8D" OR
         WHEN s577 =>
                   zw_REG_OP = X"8E" OR
            IF (rdy_i = '1') THEN
                   zw_REG_OP = X"8C")) then
               next_state <= FETCH;
               next_state <= G17_3;
            ELSE
            elsif (rdy_i = '1' and
               next_state <= s577;
                   zw_REG_OP = X"9D") then
            END IF;
               next_state <= G17_4;
         WHEN s532 =>
            elsif (rdy_i = '1' and
            IF (rdy_i = '1') THEN
                   zw_REG_OP = X"99") then
               next_state <= s533;
               next_state <= G17_4;
            ELSE
            elsif (rdy_i = '1' and
               next_state <= s532;
                   zw_REG_OP = X"91") then
            END IF;
               next_state <= G17_6;
         WHEN s533 =>
            elsif (rdy_i = '1' and
            next_state <= s534;
                   zw_REG_OP = X"81") then
         WHEN s534 =>
               next_state <= G17_8;
            next_state <= s536;
            elsif (rdy_i = '1' and
         WHEN s535 =>
                   zw_REG_OP = X"96") then
            IF (rdy_i = '1') THEN
               next_state <= G17_2;
               next_state <= s537;
            else
            ELSE
               next_state <= G17_1;
               next_state <= s535;
            end if;
            END IF;
         when G17_10 =>
         WHEN s536 =>
            next_state <= G17_e;
            next_state <= s535;
         when G17_2 =>
         WHEN s537 =>
            if (rdy_i = '1') then
            IF (rdy_i = '1') THEN
               next_state <= G17_e;
               next_state <= FETCH;
            else
            ELSE
               next_state <= G17_2;
               next_state <= s537;
            end if;
            END IF;
         when G17_3 =>
         WHEN OTHERS =>
            if (rdy_i = '1') then
 
               next_state <= G17_e;
 
            else
 
               next_state <= G17_3;
 
            end if;
 
         when G17_4 =>
 
            if (rdy_i = '1') then
 
               next_state <= G17_5;
 
            else
 
               next_state <= G17_4;
 
            end if;
 
         when G17_5 =>
 
            next_state <= G17_e;
 
         when G17_6 =>
 
            if (rdy_i = '1') then
 
               next_state <= G17_7;
 
            else
 
               next_state <= G17_6;
 
            end if;
 
         when G17_7 =>
 
            if (rdy_i = '1') then
 
               next_state <= G17_5;
 
            else
 
               next_state <= G17_7;
 
            end if;
 
         when G17_8 =>
 
            if (rdy_i = '1') then
 
               next_state <= G17_9;
 
            else
 
               next_state <= G17_8;
 
            end if;
 
         when G17_9 =>
 
            if (rdy_i = '1') then
 
               next_state <= G17_10;
 
            else
 
               next_state <= G17_9;
 
            end if;
 
         when G17_e =>
 
            next_state <= FETCH;
 
         when G18_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G18_2;
 
            else
 
               next_state <= G18_1;
 
            end if;
 
         when G18_2 =>
 
            next_state <= G18_3;
 
         when G18_3 =>
 
            next_state <= G18_4;
 
         when G18_4 =>
 
            next_state <= G18_5;
 
         when G18_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G18_e;
 
            else
 
               next_state <= G18_5;
 
            end if;
 
         when G18_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G18_e;
 
            end if;
 
         when G19_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G19_1;
 
            end if;
 
         when G1_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G1_1;
 
            end if;
 
         when G20_1 =>
 
            if (rdy_i = '1' and
 
                zw_REG_OP = X"4C") then
 
               next_state <= G20_e;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"6C") then
 
               next_state <= G20_2;
 
            else
 
               next_state <= G20_1;
 
            end if;
 
         when G20_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G20_3;
 
            else
 
               next_state <= G20_2;
 
            end if;
 
         when G20_3 =>
 
            if (rdy_i = '1') then
 
               next_state <= G20_e;
 
            else
 
               next_state <= G20_3;
 
            end if;
 
         when G20_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G20_e;
 
            end if;
 
         when G21_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G21_2;
 
            else
 
               next_state <= G21_1;
 
            end if;
 
         when G21_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G21_3;
 
            else
 
               next_state <= G21_2;
 
            end if;
 
         when G21_3 =>
 
            next_state <= G21_4;
 
         when G21_4 =>
 
            next_state <= G21_e;
 
         when G21_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G21_e;
 
            end if;
 
         when G22_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G22_e;
 
            else
 
               next_state <= G22_1;
 
            end if;
 
         when G22_e =>
 
            next_state <= FETCH;
 
         when G23_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G23_e;
 
            else
 
               next_state <= G23_1;
 
            end if;
 
         when G23_e =>
 
            next_state <= FETCH;
 
         when G24_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G24_2;
 
            else
 
               next_state <= G24_1;
 
            end if;
 
         when G24_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G24_e;
 
            else
 
               next_state <= G24_2;
 
            end if;
 
         when G24_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G24_e;
 
            end if;
 
         when G25_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G25_2;
 
            else
 
               next_state <= G25_1;
 
            end if;
 
         when G25_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G25_e;
 
            else
 
               next_state <= G25_2;
 
            end if;
 
         when G25_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G25_e;
 
            end if;
 
         when G26_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G26_2;
 
            else
 
               next_state <= G26_1;
 
            end if;
 
         when G26_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G26_3;
 
            else
 
               next_state <= G26_2;
 
            end if;
 
         when G26_3 =>
 
            if (rdy_i = '1') then
 
               next_state <= G26_4;
 
            else
 
               next_state <= G26_3;
 
            end if;
 
         when G26_4 =>
 
            if (rdy_i = '1') then
 
               next_state <= G26_e;
 
            else
 
               next_state <= G26_4;
 
            end if;
 
         when G26_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G26_e;
 
            end if;
 
         when G27_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G27_2;
 
            else
 
               next_state <= G27_1;
 
            end if;
 
         when G27_2 =>
 
            if (rdy_i = '1') then
 
               next_state <= G27_3;
 
            else
 
               next_state <= G27_2;
 
            end if;
 
         when G27_3 =>
 
            if (rdy_i = '1') then
 
               next_state <= G27_4;
 
            else
 
               next_state <= G27_3;
 
            end if;
 
         when G27_4 =>
 
            if (rdy_i = '1') then
 
               next_state <= G27_e;
 
            else
 
               next_state <= G27_4;
 
            end if;
 
         when G27_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G27_e;
 
            end if;
 
         when G28_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G28_2;
 
            else
 
               next_state <= G28_1;
 
            end if;
 
         when G28_2 =>
 
            next_state <= G28_3;
 
         when G28_3 =>
 
            next_state <= G28_4;
 
         when G28_4 =>
 
            next_state <= G28_5;
 
         when G28_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G28_e;
 
            else
 
               next_state <= G28_5;
 
            end if;
 
         when G28_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G28_e;
 
            end if;
 
         when G29_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= G29_2;
 
            else
 
               next_state <= G29_1;
 
            end if;
 
         when G29_2 =>
 
            next_state <= G29_3;
 
         when G29_3 =>
 
            next_state <= G29_4;
 
         when G29_4 =>
 
            next_state <= G29_5;
 
         when G29_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G29_e;
 
            else
 
               next_state <= G29_5;
 
            end if;
 
         when G29_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G29_e;
 
            end if;
 
         when G2_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G2_1;
 
            end if;
 
         when G30_1 =>
 
            next_state <= G30_2;
 
         when G30_2 =>
 
            next_state <= G30_3;
 
         when G30_3 =>
 
            next_state <= G30_4;
 
         when G30_4 =>
 
            next_state <= G30_5;
 
         when G30_5 =>
 
            if (rdy_i = '1') then
 
               next_state <= G30_e;
 
            else
 
               next_state <= G30_5;
 
            end if;
 
         when G30_e =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G30_e;
 
            end if;
 
         when G31_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G31_1;
 
            end if;
 
         when G32_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G32_1;
 
            end if;
 
         when G33_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G33_1;
 
            end if;
 
         when G34_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G34_1;
 
            end if;
 
         when G3_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G3_1;
 
            end if;
 
         when G4_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G4_1;
 
            end if;
 
         when G5_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G5_1;
 
            end if;
 
         when G6_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G6_1;
 
            end if;
 
         when G7_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G7_1;
 
            end if;
 
         when G8_1 =>
 
            if (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G8_1;
 
            end if;
 
         when G9_1 =>
 
            if (rdy_i = '1' and
 
                zw_REG_OP = X"9A") then
 
               next_state <= FETCH;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"BA") then
 
               next_state <= FETCH;
 
            elsif (rdy_i = '1') then
 
               next_state <= FETCH;
 
            else
 
               next_state <= G9_1;
 
            end if;
 
         when RES =>
 
            next_state <= G30_1;
 
         when others =>
            next_state <= RES;
            next_state <= RES;
      END CASE;
      end case;
   END PROCESS nextstate_proc;
   end process nextstate_proc;
 
 
   -----------------------------------------------------------------
   -----------------------------------------------------------------
   output_proc : PROCESS (
   output_proc : process (
      adr_nxt_pc_i,
      adr_nxt_pc_i,
      adr_pc_i,
      adr_pc_i,
      adr_sp_i,
      adr_sp_i,
      current_state,
      current_state,
      d_alu_i,
      d_alu_i,
Line 3386... Line 3239...
      zw_b2,
      zw_b2,
      zw_b3,
      zw_b3,
      zw_b4
      zw_b4
   )
   )
   -----------------------------------------------------------------
   -----------------------------------------------------------------
   BEGIN
   begin
      -- Default Assignment
      -- Default Assignment
      a_o <= sig_PC;
      a_o <= sig_PC;
      adr_o <= X"0000";
      adr_o <= X"0000";
      ch_a_o <= X"00";
      ch_a_o <= X"00";
      ch_b_o <= X"00";
      ch_b_o <= X"00";
Line 3408... Line 3261...
      sel_reg_o <= reg_sel_reg;
      sel_reg_o <= reg_sel_reg;
      sel_sp_as_o <= reg_sel_sp_as;
      sel_sp_as_o <= reg_sel_sp_as;
      sel_sp_in_o <= reg_sel_sp_in;
      sel_sp_in_o <= reg_sel_sp_in;
      -- Default Assignment To Internals
      -- Default Assignment To Internals
      sig_D_OUT <= X"00";
      sig_D_OUT <= X"00";
      sig_RD <= '1';
 
      sig_RWn <= '1';
 
      sig_SYNC <= '0';
      sig_SYNC <= '0';
      sig_WR <= '0';
      sig_WR <= '0';
      zw_ALU <= '0' & X"00";
      zw_ALU <= '0' & X"00";
      zw_ALU1 <= '0' & X"0";
      zw_ALU1 <= '0' & X"0";
      zw_ALU2 <= '0' & X"0";
      zw_ALU2 <= '0' & X"0";
Line 3421... Line 3272...
      zw_ALU4 <= '0' & X"0";
      zw_ALU4 <= '0' & X"0";
      zw_ALU5 <= X"0";
      zw_ALU5 <= X"0";
      zw_ALU6 <= X"0";
      zw_ALU6 <= X"0";
 
 
      -- Combined Actions
      -- Combined Actions
      CASE current_state IS
      case current_state is
         WHEN FETCH =>
         when FETCH =>
            sig_RWn <= '1';
 
            sig_RD <= '1';
 
            sig_SYNC <= NOT (rdy_i);
            sig_SYNC <= NOT (rdy_i);
            IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
            if ((nmi_i = '1') and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((irq_n_i = '0' and
            elsif ((irq_n_i = '0' and
                   reg_F(2) = '0') AND (rdy_i = '1')) THEN
                   reg_F(2) = '0') and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"69" or
            elsif ((d_i = X"69" or
                   d_i = X"65" or
                   d_i = X"65" or
                   d_i = X"75" or
                   d_i = X"75" or
                   d_i = X"6D" or
                   d_i = X"6D" or
                   d_i = X"7D" or
                   d_i = X"7D" or
                   d_i = X"79" or
                   d_i = X"79" or
                   d_i = X"61" or
                   d_i = X"61" or
                   d_i = X"71") AND (rdy_i = '1')) THEN
                   d_i = X"71") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"06" or
            elsif ((d_i = X"06" or
                   d_i = X"16" or
                   d_i = X"16" or
                   d_i = X"0E" or
                   d_i = X"0E" or
                   d_i = X"1E") AND (rdy_i = '1')) THEN
                   d_i = X"1E") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"90" or
            elsif ((d_i = X"90" or
                   d_i = X"B0" or
                   d_i = X"B0" or
                   d_i = X"F0" or
                   d_i = X"F0" or
                   d_i = X"30" or
                   d_i = X"30" or
                   d_i = X"D0" or
                   d_i = X"D0" or
                   d_i = X"10" or
                   d_i = X"10" or
                   d_i = X"50" or
                   d_i = X"50" or
                   d_i = X"70") AND (rdy_i = '1')) THEN
                   d_i = X"70") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"24" or
            elsif ((d_i = X"24" or
                   d_i = X"2C") AND (rdy_i = '1')) THEN
                   d_i = X"2C") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"00") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"18") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"D8") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"58") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"B8") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"E0" or
            elsif ((d_i = X"E0" or
                   d_i = X"E4" or
                   d_i = X"E4" or
                   d_i = X"EC") AND (rdy_i = '1')) THEN
                   d_i = X"EC") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"C0" or
            elsif ((d_i = X"C0" or
                   d_i = X"C4" or
                   d_i = X"C4" or
                   d_i = X"CC") AND (rdy_i = '1')) THEN
                   d_i = X"CC") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"C6" or
            elsif ((d_i = X"C6" or
                   d_i = X"D6" or
                   d_i = X"D6" or
                   d_i = X"CE" or
                   d_i = X"CE" or
                   d_i = X"DE") AND (rdy_i = '1')) THEN
                   d_i = X"DE") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"CA") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"88") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"49" or
            elsif ((d_i = X"49" or
                   d_i = X"45" or
                   d_i = X"45" or
                   d_i = X"55" or
                   d_i = X"55" or
                   d_i = X"4D" or
                   d_i = X"4D" or
                   d_i = X"5D" or
                   d_i = X"5D" or
                   d_i = X"59" or
                   d_i = X"59" or
Line 3531... Line 3380...
                   d_i = X"D5" or
                   d_i = X"D5" or
                   d_i = X"CD" or
                   d_i = X"CD" or
                   d_i = X"DD" or
                   d_i = X"DD" or
                   d_i = X"D9" or
                   d_i = X"D9" or
                   d_i = X"C1" or
                   d_i = X"C1" or
                   d_i = X"D1") AND (rdy_i = '1')) THEN
                   d_i = X"D1") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"E6" or
            elsif ((d_i = X"E6" or
                   d_i = X"F6" or
                   d_i = X"F6" or
                   d_i = X"EE" or
                   d_i = X"EE" or
                   d_i = X"FE") AND (rdy_i = '1')) THEN
                   d_i = X"FE") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"E8") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"C8") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"4C" or
            elsif ((d_i = X"4C" or
                   d_i = X"6C") AND (rdy_i = '1')) THEN
                   d_i = X"6C") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"20") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"A9" or
            elsif ((d_i = X"A9" or
                   d_i = X"A5" or
                   d_i = X"A5" or
                   d_i = X"B5" or
                   d_i = X"B5" or
                   d_i = X"AD" or
                   d_i = X"AD" or
                   d_i = X"BD" or
                   d_i = X"BD" or
                   d_i = X"B9" or
                   d_i = X"B9" or
                   d_i = X"A1" or
                   d_i = X"A1" or
                   d_i = X"B1") AND (rdy_i = '1')) THEN
                   d_i = X"B1") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"A2" or
            elsif ((d_i = X"A2" or
                   d_i = X"A6" or
                   d_i = X"A6" or
                   d_i = X"B6" or
                   d_i = X"B6" or
                   d_i = X"AE" or
                   d_i = X"AE" or
                   d_i = X"BE") AND (rdy_i = '1')) THEN
                   d_i = X"BE") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"A0" or
            elsif ((d_i = X"A0" or
                   d_i = X"A4" or
                   d_i = X"A4" or
                   d_i = X"B4" or
                   d_i = X"B4" or
                   d_i = X"AC" or
                   d_i = X"AC" or
                   d_i = X"BC") AND (rdy_i = '1')) THEN
                   d_i = X"BC") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"46" or
            elsif ((d_i = X"46" or
                   d_i = X"56" or
                   d_i = X"56" or
                   d_i = X"4E" or
                   d_i = X"4E" or
                   d_i = X"5E") AND (rdy_i = '1')) THEN
                   d_i = X"5E") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"EA") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"48") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"08") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"68") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"28") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"26" or
            elsif ((d_i = X"26" or
                   d_i = X"36" or
                   d_i = X"36" or
                   d_i = X"2E" or
                   d_i = X"2E" or
                   d_i = X"3E") AND (rdy_i = '1')) THEN
                   d_i = X"3E") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"66" or
            elsif ((d_i = X"66" or
                   d_i = X"76" or
                   d_i = X"76" or
                   d_i = X"6E" or
                   d_i = X"6E" or
                   d_i = X"7E") AND (rdy_i = '1')) THEN
                   d_i = X"7E") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"40") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"60") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"E9" or
            elsif ((d_i = X"E9" or
                   d_i = X"E5" or
                   d_i = X"E5" or
                   d_i = X"F5" or
                   d_i = X"F5" or
                   d_i = X"ED" or
                   d_i = X"ED" or
                   d_i = X"FD" or
                   d_i = X"FD" or
                   d_i = X"F9" or
                   d_i = X"F9" or
                   d_i = X"E1" or
                   d_i = X"E1" or
                   d_i = X"F1") AND (rdy_i = '1')) THEN
                   d_i = X"F1") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"38") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"F8") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"78") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"85" or
            elsif ((d_i = X"85" or
                   d_i = X"95" or
                   d_i = X"95" or
                   d_i = X"8D" or
                   d_i = X"8D" or
                   d_i = X"9D" or
                   d_i = X"9D" or
                   d_i = X"99" or
                   d_i = X"99" or
                   d_i = X"81" or
                   d_i = X"81" or
                   d_i = X"91") AND (rdy_i = '1')) THEN
                   d_i = X"91") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"86" or
            elsif ((d_i = X"86" or
                   d_i = X"96" or
                   d_i = X"96" or
                   d_i = X"8E") AND (rdy_i = '1')) THEN
                   d_i = X"8E") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"84" or
            elsif ((d_i = X"84" or
                   d_i = X"94" or
                   d_i = X"94" or
                   d_i = X"8C") AND (rdy_i = '1')) THEN
                   d_i = X"8C") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"AA") and (rdy_i = '1')) then
 
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"0A") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"4A") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"2A") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"6A") and (rdy_i = '1')) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"A8") and (rdy_i = '1')) then
 
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"98") and (rdy_i = '1')) then
 
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"BA") and (rdy_i = '1')) then
 
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"8A") and (rdy_i = '1')) then
 
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
            elsif ((d_i = X"9A") and (rdy_i = '1')) then
 
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF (rdy_i = '1') THEN
            elsif (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s1 =>
         when G10_1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' and
               sig_SYNC <= '1';
                zw_REG_OP = X"65") then
               fetch_o <= '1';
 
            END IF;
 
         WHEN s2 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s5 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s3 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s4 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"9A") THEN
 
               adr_o <= X"01" & d_regs_out_i;
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"BA") THEN
 
               d_regs_in_o <= adr_sp_i (7 downto 0);
 
               ch_a_o <= adr_sp_i (7 downto 0);
 
               ch_b_o <= X"00";
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF (rdy_i = '1') THEN
 
               ch_a_o <= d_regs_out_i;
 
               ch_b_o <= X"00";
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s12 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s16 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s17 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s24 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s25 =>
 
            IF (rdy_i = '1') THEN
 
               d_regs_in_o <= d_alu_i;
 
               ch_a_o <= d_regs_out_i;
 
               ch_b_o <= zw_b4;
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s273 =>
 
            IF (rdy_i = '1') THEN
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            elsif (rdy_i = '1' and
         WHEN s307 =>
                   zw_REG_OP = X"69" and
            IF (rdy_i = '1') THEN
                   reg_F(3) = '0') then
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            elsif (rdy_i = '1' and
         WHEN s177 =>
                   zw_REG_OP = X"75") then
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"85" OR
 
                zw_REG_OP = X"86" OR
 
                zw_REG_OP = X"84")) THEN
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
               sig_D_OUT <= d_regs_out_i;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"95" OR
 
                   zw_REG_OP = X"94")) THEN
 
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"8D" OR
                   zw_REG_OP = X"6D") then
                   zw_REG_OP = X"8E" OR
 
                   zw_REG_OP = X"8C")) THEN
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"9D") THEN
                   zw_REG_OP = X"7D") then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"99") THEN
                   zw_REG_OP = X"79") then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"91") THEN
                   zw_REG_OP = X"71") then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"01";
               ch_b_o <= X"01";
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"81") THEN
                   zw_REG_OP = X"61") then
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"96") THEN
                   zw_REG_OP = X"69" and
               ch_a_o <=  d_i;
                   reg_F(3) = '1') then
               ch_b_o <= q_y_i;
               ld_o <= "11";
            END IF;
               ld_pc_o <= '1';
         WHEN s180 =>
               d_regs_in_o <= zw_ALU(7 downto 0);
            IF (rdy_i = '1') THEN
               load_regs_o <= '1';
 
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
 
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
 
 
 
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
 
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
 
 
 
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
 
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
 
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
 
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G10_2 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G10_3 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G10_4 =>
 
            if (rdy_i = '1') then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= "0000000" & zw_b2(0);
               ch_b_o <= X"01";
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s181 =>
         when G10_5 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            END IF;
            end if;
         WHEN s182 =>
         when G10_6 =>
            sig_RWn <= '1';
            if (rdy_i = '1') then
            sig_RD <= '1';
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= "0000000" & zw_b2(0);
               ch_b_o <= X"01";
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s183 =>
 
            IF (rdy_i = '1') THEN
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
               sig_D_OUT <= d_regs_out_i;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s184 =>
         when G10_e1 =>
 
            if (rdy_i = '1' AND
 
                zw_b2(0) = '0' and
 
                reg_F(3) = '0') then
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
            sig_SYNC <= '1';
            sig_SYNC <= '1';
            fetch_o <= '1';
            fetch_o <= '1';
         WHEN s185 =>
            elsif (rdy_i = '1' AND
            IF (rdy_i = '1') THEN
                   zw_b2(0) = '0' and
               sig_RWn <= '0';
                   reg_F(3) = '1') then
               sig_RD <= '0';
               d_regs_in_o <= zw_ALU(7 downto 0);
               sig_WR <= '1';
               load_regs_o <= '1';
               sig_D_OUT <= d_regs_out_i;
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
               ld_o <= "11";
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
               ld_pc_o <= '1';
 
            END IF;
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
         WHEN s187 =>
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
 
 
 
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
 
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
 
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
 
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G10_e2 =>
 
            if (rdy_i = '1' and
 
                reg_F(3) = '0') then
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
            sig_SYNC <= '1';
            sig_SYNC <= '1';
            fetch_o <= '1';
            fetch_o <= '1';
         WHEN s188 =>
            elsif (rdy_i = '1' and
            IF (rdy_i = '1') THEN
                   reg_F(3) = '1') then
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
 
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
 
 
 
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
 
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
 
 
 
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
 
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
 
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
 
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G10_e3 =>
 
            if (rdy_i = '1') then
               ch_a_o <=  zw_b1;
               ch_a_o <=  zw_b1;
               ch_b_o <= X"01";
               ch_b_o <= X"01";
            END IF;
            end if;
         WHEN s189 =>
         when G11_1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' and
 
                (zw_REG_OP = X"1E" or
 
                zw_REG_OP = X"7E" or
 
                zw_REG_OP = X"3E" or
 
                zw_REG_OP = X"5E")) then
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= "0000000" & zw_b2(0);
               ch_b_o <= q_x_i;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"06" or
 
                   zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"46")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            elsif (rdy_i = '1' and
         WHEN s190 =>
                   (zw_REG_OP = X"16" or
            sig_SYNC <= '1';
                   zw_REG_OP = X"76" or
            fetch_o <= '1';
                   zw_REG_OP = X"36" or
         WHEN s191 =>
                   zw_REG_OP = X"56")) then
            sig_RWn <= '0';
               ch_a_o <=  d_i;
            sig_RD <= '0';
               ch_b_o <= q_x_i;
            sig_WR <= '1';
            elsif (rdy_i = '1' and
            sig_D_OUT <= d_regs_out_i;
                   (zw_REG_OP = X"0E" or
         WHEN s192 =>
                   zw_REG_OP = X"6E" or
            sig_RWn <= '0';
                   zw_REG_OP = X"2E" or
            sig_RD <= '0';
                   zw_REG_OP = X"4E")) then
            sig_WR <= '1';
 
            sig_D_OUT <= d_regs_out_i;
 
            ld_o <= "11";
            ld_o <= "11";
            ld_pc_o <= '1';
            ld_pc_o <= '1';
         WHEN s193 =>
            end if;
            sig_SYNC <= '1';
         when G11_2 =>
            fetch_o <= '1';
            if (rdy_i = '1') then
         WHEN s377 =>
 
            IF (rdy_i = '1') THEN
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
               sig_D_OUT <= q_a_i;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s381 =>
         when G11_4 =>
            sig_SYNC <= '1';
            if (rdy_i = '1' and
            fetch_o <= '1';
                (zw_REG_OP = X"06" or
         WHEN s378 =>
                zw_REG_OP = X"16" or
            IF (rdy_i = '1') THEN
                zw_REG_OP = X"0E" or
               sig_RWn <= '0';
                zw_REG_OP = X"1E")) then
               sig_RD <= '0';
               sig_D_OUT <= d_i(6 downto 0) & '0';
               sig_WR <= '1';
               sig_WR <= '1';
               sig_D_OUT <= reg_F;
            elsif (rdy_i = '1' and
               ld_o <= "11";
                   (zw_REG_OP = X"46" or
               ld_sp_o <= '1';
                   zw_REG_OP = X"56" or
            END IF;
                   zw_REG_OP = X"4E" or
         WHEN s382 =>
                   zw_REG_OP = X"5E")) then
            sig_SYNC <= '1';
               sig_D_OUT <= '0' & d_i(7 downto 1);
            fetch_o <= '1';
               sig_WR <= '1';
         WHEN s379 =>
            elsif (rdy_i = '1' and
            IF (rdy_i = '1') THEN
                   (zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"3E")) then
 
               sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
 
               sig_WR <= '1';
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"7E")) then
 
               sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
 
               sig_WR <= '1';
 
            end if;
 
         when G11_5 =>
 
            if (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s384 =>
         when G11_6 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               d_regs_in_o <= d_i;
 
               load_regs_o <= '1';
 
               ch_a_o <= d_i;
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G11_e =>
 
            ch_a_o <= zw_b1;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
         when G12_1 =>
         WHEN s380 =>
            if (rdy_i = '1' and (
            IF (rdy_i = '1') THEN
                (reg_F(0) = '1' and zw_REG_OP = X"90") or
 
                (reg_F(0) = '0' and zw_REG_OP = X"B0") or
 
                (reg_F(1) = '0' and zw_REG_OP = X"F0") or
 
                (reg_F(7) = '0' and zw_REG_OP = X"30") or
 
                (reg_F(1) = '1' and zw_REG_OP = X"D0") or
 
                (reg_F(7) = '1' and zw_REG_OP = X"10") or
 
                (reg_F(6) = '1' and zw_REG_OP = X"50") or
 
                (reg_F(6) = '0' and zw_REG_OP = X"70"))) then
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
               ld_pc_o <= '1';
            END IF;
 
         WHEN s386 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            elsif (rdy_i = '1') then
         WHEN s387 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            END IF;
 
         WHEN s388 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            END IF;
 
         WHEN s389 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s392 =>
         when G12_e1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' and
               adr_o <= d_i & zw_b1;
                zw_b3 = adr_nxt_pc_i (15 downto 8)) then
 
               offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
 
               zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            elsif (rdy_i = '1') then
         WHEN s390 =>
               offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
            IF (rdy_i = '1') THEN
               zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            END IF;
 
         WHEN s393 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            END IF;
 
         WHEN s395 =>
 
            IF (rdy_i = '1') THEN
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s396 =>
         when G12_e2 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s397 =>
         when G13_1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' and
 
                zw_REG_OP = X"24") then
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
 
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            elsif (rdy_i = '1' and
         WHEN s398 =>
                   zw_REG_OP = X"2C") then
            IF (rdy_i = '1') THEN
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
               sig_D_OUT <= adr_pc_i (15 downto 8);
 
            END IF;
 
         WHEN s399 =>
 
            ld_o <= "11";
            ld_o <= "11";
            ld_sp_o <= '1';
               ld_pc_o <= '1';
            sig_RWn <= '0';
            end if;
            sig_RD <= '0';
         when G13_2 =>
            sig_WR <= '1';
            if (rdy_i = '1') then
            sig_D_OUT <= adr_pc_i (7 downto 0);
 
         WHEN s401 =>
 
            IF (rdy_i = '1') THEN
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
 
            end if;
 
         when G13_e =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= q_a_i AND d_i;
 
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s526 =>
         when G14_1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' and
 
                (zw_REG_OP = X"C6" OR
 
                zw_REG_OP = X"E6")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
 
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_RWn <= '0';
            elsif (rdy_i = '1' and
               sig_RD <= '0';
                   (zw_REG_OP = X"D6" OR
               sig_WR <= '1';
                   zw_REG_OP = X"F6")) then
               sig_D_OUT <= adr_pc_i (15 downto 8);
               ch_a_o <=  d_i;
            END IF;
               ch_b_o <= q_x_i;
         WHEN s527 =>
            elsif (rdy_i = '1' and
            ld_o <= "11";
                   (zw_REG_OP = X"CE" OR
            ld_sp_o <= '1';
                   zw_REG_OP = X"EE")) then
            sig_RWn <= '0';
 
            sig_RD <= '0';
 
            sig_WR <= '1';
 
            sig_D_OUT <= adr_pc_i (7 downto 0);
 
         WHEN s528 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
            sig_RWn <= '0';
 
            sig_RD <= '0';
 
            sig_WR <= '1';
 
            sig_D_OUT <= reg_F OR X"10";
 
         WHEN s530 =>
 
            IF (rdy_i = '1') THEN
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_SYNC <= '1';
            elsif (rdy_i = '1' and
               fetch_o <= '1';
                   (zw_REG_OP = X"DE" OR
            END IF;
                   zw_REG_OP = X"FE")) then
         WHEN s544 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
         WHEN s545 =>
 
            adr_o <= X"FFFB";
 
            ld_o <= "11";
            ld_o <= "11";
            ld_pc_o <= '1';
            ld_pc_o <= '1';
         WHEN s546 =>
               ch_a_o <= d_i;
 
               ch_b_o <= q_x_i;
 
            end if;
 
         when G14_2 =>
 
            if (rdy_i = '1') then
            ld_o <= "11";
            ld_o <= "11";
            ld_pc_o <= '1';
            ld_pc_o <= '1';
         WHEN s549 =>
            end if;
            IF (rdy_i = '1') THEN
         when G14_3 =>
               adr_o <= d_i & zw_b1;
            if (rdy_i = '1') then
 
               ch_a_o <= d_i;
 
               ch_b_o <= zw_b4;
 
            end if;
 
         when G14_4 =>
 
            if (rdy_i = '1') then
 
               sig_WR <= '1';
 
               sig_D_OUT <= zw_b1;
 
            end if;
 
         when G14_5 =>
 
            if (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_SYNC <= '1';
            end if;
               fetch_o <= '1';
         when G14_6 =>
            END IF;
            if (rdy_i = '1') then
         WHEN s550 =>
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
            ld_o <= "11";
            ld_o <= "11";
            ld_sp_o <= '1';
               ld_pc_o <= '1';
         WHEN s404 =>
            end if;
            IF (rdy_i = '1') THEN
         when G14_e =>
               ch_a_o <= q_a_i (6 downto 0) & '0';
            ch_a_o <= zw_b1;
               ch_b_o <= X"00";
 
               d_regs_in_o <= q_a_i (6 downto 0) & '0';
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s556 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= '0' & q_a_i (7 downto 1);
 
               ch_b_o <= X"00";
 
               d_regs_in_o <= '0' & q_a_i (7 downto 1);
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s557 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
 
               ch_b_o <= X"00";
 
               d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s579 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
 
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
         when G15_1 =>
         WHEN s201 =>
            if (rdy_i = '1' and
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
                (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
                zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
                zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
                zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
                zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
                zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
                zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF ((rdy_i = '1' and
            elsif ((rdy_i = '1' and
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               d_regs_in_o <= d_i OR q_a_i;
               d_regs_in_o <= d_i OR q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i OR q_a_i;
               ch_a_o <= d_i OR q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1' and
            elsif ((rdy_i = '1' and
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               d_regs_in_o <= d_i XOR q_a_i;
               d_regs_in_o <= d_i XOR q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i XOR q_a_i;
               ch_a_o <= d_i XOR q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1' and
            elsif ((rdy_i = '1' and
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               d_regs_in_o <= d_i AND q_a_i;
               d_regs_in_o <= d_i AND q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i AND q_a_i;
               ch_a_o <= d_i AND q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1' and
            elsif ((rdy_i = '1' and
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               d_regs_in_o <= d_i;
               d_regs_in_o <= d_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"B5" OR
                   (zw_REG_OP = X"B5" OR
                   zw_REG_OP = X"B4" OR
                   zw_REG_OP = X"B4" OR
                   zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
                   zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
                   zw_REG_OP = X"35" OR
                   zw_REG_OP = X"35" OR
                   zw_REG_OP = X"D5")) THEN
                   zw_REG_OP = X"D5")) then
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"AD" OR
                   (zw_REG_OP = X"AD" OR
                   zw_REG_OP = X"AE" OR
                   zw_REG_OP = X"AE" OR
                   zw_REG_OP = X"AC" OR
                   zw_REG_OP = X"AC" OR
                   zw_REG_OP = X"4D" OR
                   zw_REG_OP = X"4D" OR
                   zw_REG_OP = X"0D" OR
                   zw_REG_OP = X"0D" OR
                   zw_REG_OP = X"2D" OR
                   zw_REG_OP = X"2D" OR
                   zw_REG_OP = X"CD" OR
                   zw_REG_OP = X"CD" OR
                   zw_REG_OP = X"EC" OR
                   zw_REG_OP = X"EC" OR
                   zw_REG_OP = X"CC")) THEN
                   zw_REG_OP = X"CC")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"BD" OR
                   (zw_REG_OP = X"BD" OR
                   zw_REG_OP = X"BC" OR
                   zw_REG_OP = X"BC" OR
                   zw_REG_OP = X"5D" OR
                   zw_REG_OP = X"5D" OR
                   zw_REG_OP = X"1D" OR
                   zw_REG_OP = X"1D" OR
                   zw_REG_OP = X"3D" OR
                   zw_REG_OP = X"3D" OR
                   zw_REG_OP = X"DD")) THEN
                   zw_REG_OP = X"DD")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"B9" OR
                   (zw_REG_OP = X"B9" OR
                   zw_REG_OP = X"BE" OR
                   zw_REG_OP = X"BE" OR
                   zw_REG_OP = X"59" OR
                   zw_REG_OP = X"59" OR
                   zw_REG_OP = X"19" OR
                   zw_REG_OP = X"19" OR
                   zw_REG_OP = X"39" OR
                   zw_REG_OP = X"39" OR
                   zw_REG_OP = X"D9")) THEN
                   zw_REG_OP = X"D9")) then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"B1" OR
                   (zw_REG_OP = X"B1" OR
                   zw_REG_OP = X"51" OR
                   zw_REG_OP = X"51" OR
                   zw_REG_OP = X"11" OR
                   zw_REG_OP = X"11" OR
                   zw_REG_OP = X"31" OR
                   zw_REG_OP = X"31" OR
                   zw_REG_OP = X"D1")) THEN
                   zw_REG_OP = X"D1")) then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"01";
               ch_b_o <= X"01";
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   (zw_REG_OP = X"A1" OR
                   (zw_REG_OP = X"A1" OR
                   zw_REG_OP = X"41" OR
                   zw_REG_OP = X"41" OR
                   zw_REG_OP = X"01" OR
                   zw_REG_OP = X"01" OR
                   zw_REG_OP = X"21" OR
                   zw_REG_OP = X"21" OR
                   zw_REG_OP = X"C1")) THEN
                   zw_REG_OP = X"C1")) then
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"B6") THEN
                   zw_REG_OP = X"B6") then
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            END IF;
            end if;
         WHEN s202 =>
         when G15_2 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s210 =>
         when G15_3 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s211 =>
         when G15_4 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= "0000000" & zw_b2(0);
               ch_b_o <= "0000000" & zw_b2(0);
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s215 =>
         when G15_5 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            END IF;
            end if;
         WHEN s217 =>
         when G15_6 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s222 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <=  zw_b1;
 
               ch_b_o <= X"01";
 
            END IF;
 
         WHEN s223 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= "0000000" & zw_b2(0);
               ch_b_o <= "0000000" & zw_b2(0);
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s224 =>
         when G15_e1 =>
            IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
            if ((rdy_i = '1' AND
 
                zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
               d_regs_in_o <= d_i OR q_a_i;
               d_regs_in_o <= d_i OR q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i OR q_a_i;
               ch_a_o <= d_i OR q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
            elsif ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
               d_regs_in_o <= d_i XOR q_a_i;
               d_regs_in_o <= d_i XOR q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i XOR q_a_i;
               ch_a_o <= d_i XOR q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
            elsif ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
               d_regs_in_o <= d_i AND q_a_i;
               d_regs_in_o <= d_i AND q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i AND q_a_i;
               ch_a_o <= d_i AND q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
            elsif ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1') THEN
            elsif (rdy_i = '1' AND
 
                   zw_b2(0) = '0') then
               d_regs_in_o <= d_i;
               d_regs_in_o <= d_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s225 =>
         when G15_e2 =>
            IF ((rdy_i = '1' AND
            if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
                zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
 
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
               d_regs_in_o <= d_i OR q_a_i;
               d_regs_in_o <= d_i OR q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i OR q_a_i;
               ch_a_o <= d_i OR q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1' AND
            elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
                   zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
 
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
               d_regs_in_o <= d_i XOR q_a_i;
               d_regs_in_o <= d_i XOR q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i XOR q_a_i;
               ch_a_o <= d_i XOR q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF ((rdy_i = '1' AND
            elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
                   zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
 
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
               d_regs_in_o <= d_i AND q_a_i;
               d_regs_in_o <= d_i AND q_a_i;
               load_regs_o <= '1';
               load_regs_o <= '1';
               ch_a_o <= d_i AND q_a_i;
               ch_a_o <= d_i AND q_a_i;
               ch_b_o <= X"00";
               ch_b_o <= X"00";
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF ((rdy_i = '1' AND
 
                   zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
 
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
 
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
 
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
 
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
 
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
 
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
 
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF (rdy_i = '1' AND
 
                   zw_b2(0) = '0') THEN
 
               d_regs_in_o <= d_i;
 
               load_regs_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= X"00";
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s226 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"C6" OR
 
                zw_REG_OP = X"E6")) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"D6" OR
 
                   zw_REG_OP = X"F6")) THEN
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_x_i;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"CE" OR
 
                   zw_REG_OP = X"EE")) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"DE" OR
 
                   zw_REG_OP = X"FE")) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_x_i;
 
            END IF;
 
         WHEN s243 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s244 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s247 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s343 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= zw_b4;
 
            END IF;
 
         WHEN s250 =>
 
            IF (rdy_i = '1') THEN
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
               sig_D_OUT <= zw_b1;
 
            END IF;
 
         WHEN s251 =>
 
            ch_a_o <= zw_b1;
 
            ch_b_o <= X"00";
 
            sig_SYNC <= '1';
 
            fetch_o <= '1';
 
         WHEN s351 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"24") THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"2C") THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s361 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= q_a_i AND d_i;
 
               ch_b_o <= X"00";
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s360 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s403 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"1E" or
 
                zw_REG_OP = X"7E" or
 
                zw_REG_OP = X"3E" or
 
                zw_REG_OP = X"5E")) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_x_i;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"06" or
 
                   zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"46")) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"16" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"56")) THEN
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_x_i;
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"0E" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"4E")) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s406 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s407 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s409 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s416 =>
 
            IF (rdy_i = '1' and
 
                (zw_REG_OP = X"06" or
 
                zw_REG_OP = X"16" or
 
                zw_REG_OP = X"0E" or
 
                zw_REG_OP = X"1E")) THEN
 
               sig_D_OUT <= d_i(6 downto 0) & '0';
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"46" or
 
                   zw_REG_OP = X"56" or
 
                   zw_REG_OP = X"4E" or
 
                   zw_REG_OP = X"5E")) THEN
 
               sig_D_OUT <= '0' & d_i(7 downto 1);
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"26" or
 
                   zw_REG_OP = X"36" or
 
                   zw_REG_OP = X"2E" or
 
                   zw_REG_OP = X"3E")) THEN
 
               sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   (zw_REG_OP = X"66" or
 
                   zw_REG_OP = X"76" or
 
                   zw_REG_OP = X"6E" or
 
                   zw_REG_OP = X"7E")) THEN
 
               sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
 
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
 
            END IF;
 
         WHEN s418 =>
 
            ch_a_o <= zw_b1;
 
            ch_b_o <= X"00";
 
            sig_SYNC <= '1';
 
            fetch_o <= '1';
 
         WHEN s510 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"65") THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"69" and
 
                   reg_F(3) = '0') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"75") THEN
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_x_i;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"6D") THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"7D") THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_x_i;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"79") THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_y_i;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"71") THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= X"01";
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"61") THEN
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_x_i;
 
            ELSIF (rdy_i = '1' and
 
                   zw_REG_OP = X"69" and
 
                   reg_F(3) = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
 
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
 
 
 
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
 
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
 
 
 
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
 
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
 
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
 
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s553 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s555 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= X"01";
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s558 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_y_i;
 
            END IF;
 
         WHEN s560 =>
 
            IF (rdy_i = '1') THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s563 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <=  zw_b1;
 
               ch_b_o <= X"01";
 
            END IF;
 
         WHEN s564 =>
 
            IF (rdy_i = '1' AND
 
                zw_b2(0) = '0' and
 
                reg_F(3) = '0') THEN
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF (rdy_i = '1' AND
 
                   zw_b2(0) = '0' and
 
                   reg_F(3) = '1') THEN
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
 
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
 
 
 
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
 
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
 
 
 
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
 
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
 
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
 
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s565 =>
 
            IF (rdy_i = '1' and
 
                reg_F(3) = '0') THEN
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            ELSIF (rdy_i = '1' and
 
                   reg_F(3) = '1') THEN
 
               d_regs_in_o <= zw_ALU(7 downto 0);
 
               load_regs_o <= '1';
 
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
 
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
 
 
 
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
 
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
 
 
 
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
 
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
 
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
 
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            END IF;
 
         WHEN s566 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
 
               ch_b_o <= X"01";
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s266 =>
 
            IF (rdy_i = '1' and (
 
                (reg_F(0) = '1' and zw_REG_OP = X"90") or
 
                (reg_F(0) = '0' and zw_REG_OP = X"B0") or
 
                (reg_F(1) = '0' and zw_REG_OP = X"F0") or
 
                (reg_F(7) = '0' and zw_REG_OP = X"30") or
 
                (reg_F(1) = '1' and zw_REG_OP = X"D0") or
 
                (reg_F(7) = '1' and zw_REG_OP = X"10") or
 
                (reg_F(6) = '1' and zw_REG_OP = X"50") or
 
                (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1') THEN
            elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
               ld_o <= "11";
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
               ld_pc_o <= '1';
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
            END IF;
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
         WHEN s301 =>
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
            IF (rdy_i = '1' and
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
                zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
               offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
               zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1') THEN
            elsif (rdy_i = '1') then
               offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
               d_regs_in_o <= d_i;
               zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
               load_regs_o <= '1';
               ld_o <= "11";
               ch_a_o <= d_i;
               ld_pc_o <= '1';
               ch_b_o <= X"00";
            END IF;
 
         WHEN s302 =>
 
            IF (rdy_i = '1') THEN
 
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN RES =>
         when G15_e3 =>
            sig_RWn <= '1';
            if (rdy_i = '1') then
            sig_RD <= '1';
               ch_a_o <=  zw_b1;
            ld_o <= "11";
               ch_b_o <= X"01";
            ld_pc_o <= '1';
            end if;
 
         when G16_1 =>
            ld_sp_o <= '1';
            if (rdy_i = '1' and
            sig_RWn <= '1';
                zw_REG_OP = X"E5") then
            sig_RD <= '1';
 
         WHEN s511 =>
 
            IF (rdy_i = '1' and
 
                zw_REG_OP = X"E5") THEN
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"E9" and
                   zw_REG_OP = X"E9" and
                   reg_F(3) = '0') THEN
                   reg_F(3) = '0') then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               d_regs_in_o <= zw_ALU(7 downto 0);
               d_regs_in_o <= zw_ALU(7 downto 0);
               load_regs_o <= '1';
               load_regs_o <= '1';
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"F5") THEN
                   zw_REG_OP = X"F5") then
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"ED") THEN
                   zw_REG_OP = X"ED") then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"FD") THEN
                   zw_REG_OP = X"FD") then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"F9") THEN
                   zw_REG_OP = X"F9") then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"F1") THEN
                   zw_REG_OP = X"F1") then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"01";
               ch_b_o <= X"01";
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"E1") THEN
                   zw_REG_OP = X"E1") then
               ch_a_o <=  d_i;
               ch_a_o <=  d_i;
               ch_b_o <= q_x_i;
               ch_b_o <= q_x_i;
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   zw_REG_OP = X"E9" and
                   zw_REG_OP = X"E9" and
                   reg_F(3) = '1') THEN
                   reg_F(3) = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               d_regs_in_o <= zw_ALU(7 downto 0);
               d_regs_in_o <= zw_ALU(7 downto 0);
               load_regs_o <= '1';
               load_regs_o <= '1';
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
Line 4827... Line 4227...
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s559 =>
         when G16_2 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s562 =>
         when G16_3 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
 
               ch_b_o <= X"01";
 
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s567 =>
         when G16_4 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"01";
               ch_b_o <= X"01";
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s568 =>
         when G16_5 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= q_y_i;
               ch_b_o <= q_y_i;
            END IF;
            end if;
         WHEN s569 =>
         when G16_6 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            END IF;
 
         WHEN s571 =>
 
            IF (rdy_i = '1') THEN
 
               ch_a_o <= d_i;
               ch_a_o <= d_i;
               ch_b_o <= X"01";
               ch_b_o <= X"01";
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
            END IF;
            end if;
         WHEN s572 =>
         when G16_e1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1' AND
               ch_a_o <=  zw_b1;
 
               ch_b_o <= X"01";
 
            END IF;
 
         WHEN s573 =>
 
            IF (rdy_i = '1' AND
 
                zw_b2(0) = '0' and
                zw_b2(0) = '0' and
                reg_F(3) = '0') THEN
                reg_F(3) = '0') then
               d_regs_in_o <= zw_ALU(7 downto 0);
               d_regs_in_o <= zw_ALU(7 downto 0);
               load_regs_o <= '1';
               load_regs_o <= '1';
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1' AND
            elsif (rdy_i = '1' AND
                   zw_b2(0) = '0' and
                   zw_b2(0) = '0' and
                   reg_F(3) = '1') THEN
                   reg_F(3) = '1') then
               d_regs_in_o <= zw_ALU(7 downto 0);
               d_regs_in_o <= zw_ALU(7 downto 0);
               load_regs_o <= '1';
               load_regs_o <= '1';
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
 
 
Line 4896... Line 4284...
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s574 =>
         when G16_e2 =>
            IF (rdy_i = '1' and
            if (rdy_i = '1' and
                reg_F(3) = '0') THEN
                reg_F(3) = '0') then
               d_regs_in_o <= zw_ALU(7 downto 0);
               d_regs_in_o <= zw_ALU(7 downto 0);
               load_regs_o <= '1';
               load_regs_o <= '1';
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            ELSIF (rdy_i = '1' and
            elsif (rdy_i = '1' and
                   reg_F(3) = '1') THEN
                   reg_F(3) = '1') then
               d_regs_in_o <= zw_ALU(7 downto 0);
               d_regs_in_o <= zw_ALU(7 downto 0);
               load_regs_o <= '1';
               load_regs_o <= '1';
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
 
 
Line 4922... Line 4310...
 
 
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s548 =>
         when G16_e3 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
 
               ch_a_o <=  zw_b1;
 
               ch_b_o <= X"01";
 
            end if;
 
         when G17_1 =>
 
            if (rdy_i = '1' and
 
                (zw_REG_OP = X"85" OR
 
                zw_REG_OP = X"86" OR
 
                zw_REG_OP = X"84")) then
 
               sig_WR <= '1';
 
               sig_D_OUT <= d_regs_out_i;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"95" OR
 
                   zw_REG_OP = X"94")) then
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_x_i;
 
            elsif (rdy_i = '1' and
 
                   (zw_REG_OP = X"8D" OR
 
                   zw_REG_OP = X"8E" OR
 
                   zw_REG_OP = X"8C")) then
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"9D") then
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_x_i;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"99") then
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_y_i;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"91") then
 
               ch_a_o <= d_i;
 
               ch_b_o <= X"01";
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"81") then
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_x_i;
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"96") then
 
               ch_a_o <=  d_i;
 
               ch_b_o <= q_y_i;
 
            end if;
 
         when G17_10 =>
 
            sig_WR <= '1';
 
            sig_D_OUT <= d_regs_out_i;
 
            ld_o <= "11";
 
            ld_pc_o <= '1';
 
         when G17_2 =>
 
            if (rdy_i = '1') then
 
               sig_WR <= '1';
 
               sig_D_OUT <= d_regs_out_i;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G17_3 =>
 
            if (rdy_i = '1') then
 
               sig_WR <= '1';
 
               sig_D_OUT <= d_regs_out_i;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G17_4 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G17_5 =>
 
            sig_WR <= '1';
 
            sig_D_OUT <= d_regs_out_i;
 
         when G17_6 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= d_i;
 
               ch_b_o <= q_y_i;
 
            end if;
 
         when G17_7 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= d_i;
 
               ch_b_o <= "0000000" & zw_b2(0);
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G17_9 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <=  zw_b1;
 
               ch_b_o <= X"01";
 
            end if;
 
         when G17_e =>
 
            sig_SYNC <= '1';
 
            fetch_o <= '1';
 
         when G18_1 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
               ld_pc_o <= '1';
 
               sig_WR <= '1';
 
               sig_D_OUT <= adr_pc_i (15 downto 8);
 
            end if;
 
         when G18_2 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
            sig_WR <= '1';
 
            sig_D_OUT <= adr_pc_i (7 downto 0);
 
         when G18_3 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
            sig_WR <= '1';
 
            sig_D_OUT <= reg_F OR X"10";
 
         when G18_e =>
 
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G19_1 =>
 
            if (rdy_i = '1') then
 
               d_regs_in_o <= d_alu_i;
 
               ch_a_o <= d_regs_out_i;
 
               ch_b_o <= zw_b4;
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G1_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G20_2 =>
 
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G20_e =>
 
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G21_1 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
               ld_pc_o <= '1';
 
            end if;
 
         when G21_2 =>
 
            if (rdy_i = '1') then
 
               sig_WR <= '1';
 
               sig_D_OUT <= adr_pc_i (15 downto 8);
 
            end if;
 
         when G21_3 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
            sig_WR <= '1';
 
            sig_D_OUT <= adr_pc_i (7 downto 0);
 
         when G21_e =>
 
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G22_1 =>
 
            if (rdy_i = '1') then
 
               sig_WR <= '1';
 
               sig_D_OUT <= q_a_i;
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G22_e =>
 
            sig_SYNC <= '1';
 
            fetch_o <= '1';
 
         when G23_1 =>
 
            if (rdy_i = '1') then
 
               sig_WR <= '1';
 
               sig_D_OUT <= reg_F;
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G23_e =>
 
            sig_SYNC <= '1';
 
            fetch_o <= '1';
 
         when G24_1 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G24_e =>
 
            if (rdy_i = '1') then
 
               d_regs_in_o <= d_i;
 
               load_regs_o <= '1';
 
               ch_a_o <= d_i;
 
               ch_b_o <= X"00";
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G25_1 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G25_e =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G26_1 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G26_2 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G26_3 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G26_e =>
 
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G27_1 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G27_2 =>
 
            if (rdy_i = '1') then
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
            end if;
 
         when G27_4 =>
 
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
            end if;
 
         when G27_e =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G28_1 =>
 
            if (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
               ld_sp_o <= '1';
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
               sig_WR <= '1';
               sig_D_OUT <= adr_pc_i (15 downto 8);
               sig_D_OUT <= adr_pc_i (15 downto 8);
            END IF;
            end if;
         WHEN s551 =>
         when G28_2 =>
            ld_o <= "11";
            ld_o <= "11";
            ld_sp_o <= '1';
            ld_sp_o <= '1';
            sig_RWn <= '0';
 
            sig_RD <= '0';
 
            sig_WR <= '1';
            sig_WR <= '1';
            sig_D_OUT <= adr_pc_i (7 downto 0);
            sig_D_OUT <= adr_pc_i (7 downto 0);
         WHEN s552 =>
         when G28_3 =>
            ld_o <= "11";
            ld_o <= "11";
            ld_sp_o <= '1';
            ld_sp_o <= '1';
            sig_RWn <= '0';
 
            sig_RD <= '0';
 
            sig_WR <= '1';
            sig_WR <= '1';
            sig_D_OUT <= reg_F;
            sig_D_OUT <= reg_F;
         WHEN s577 =>
         when G28_e =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN s532 =>
         when G29_1 =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
               ld_o <= "11";
               ld_o <= "11";
               ld_sp_o <= '1';
               ld_sp_o <= '1';
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_RWn <= '0';
 
               sig_RD <= '0';
 
               sig_WR <= '1';
               sig_WR <= '1';
               sig_D_OUT <= adr_pc_i (15 downto 8);
               sig_D_OUT <= adr_pc_i (15 downto 8);
            END IF;
            end if;
         WHEN s533 =>
         when G29_2 =>
            ld_o <= "11";
            ld_o <= "11";
            ld_sp_o <= '1';
            ld_sp_o <= '1';
            sig_RWn <= '0';
 
            sig_RD <= '0';
 
            sig_WR <= '1';
            sig_WR <= '1';
            sig_D_OUT <= adr_pc_i (7 downto 0);
            sig_D_OUT <= adr_pc_i (7 downto 0);
         WHEN s534 =>
         when G29_3 =>
            ld_o <= "11";
            ld_o <= "11";
            ld_sp_o <= '1';
            ld_sp_o <= '1';
            sig_RWn <= '0';
 
            sig_RD <= '0';
 
            sig_WR <= '1';
            sig_WR <= '1';
            sig_D_OUT <= reg_F;
            sig_D_OUT <= reg_F;
         WHEN s537 =>
         when G29_e =>
            IF (rdy_i = '1') THEN
            if (rdy_i = '1') then
 
               adr_o <= d_i & zw_b1;
 
               ld_o <= "11";
 
               ld_pc_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G2_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G30_1 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
         when G30_2 =>
 
            ld_o <= "11";
 
            ld_sp_o <= '1';
 
         when G30_3 =>
 
            adr_o <= X"FFFB";
 
            ld_o <= "11";
 
            ld_pc_o <= '1';
 
         when G30_4 =>
 
            ld_o <= "11";
 
            ld_pc_o <= '1';
 
         when G30_e =>
 
            if (rdy_i = '1') then
               adr_o <= d_i & zw_b1;
               adr_o <= d_i & zw_b1;
               ld_o <= "11";
               ld_o <= "11";
               ld_pc_o <= '1';
               ld_pc_o <= '1';
               sig_SYNC <= '1';
               sig_SYNC <= '1';
               fetch_o <= '1';
               fetch_o <= '1';
            END IF;
            end if;
         WHEN OTHERS =>
         when G31_1 =>
            NULL;
            if (rdy_i = '1') then
      END CASE;
               ch_a_o <= q_a_i (6 downto 0) & '0';
   END PROCESS output_proc;
               ch_b_o <= X"00";
 
               d_regs_in_o <= q_a_i (6 downto 0) & '0';
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G32_1 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= '0' & q_a_i (7 downto 1);
 
               ch_b_o <= X"00";
 
               d_regs_in_o <= '0' & q_a_i (7 downto 1);
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G33_1 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
 
               ch_b_o <= X"00";
 
               d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G34_1 =>
 
            if (rdy_i = '1') then
 
               ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
 
               ch_b_o <= X"00";
 
               d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G3_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G4_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G5_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G6_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G7_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G8_1 =>
 
            if (rdy_i = '1') then
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when G9_1 =>
 
            if (rdy_i = '1' and
 
                zw_REG_OP = X"9A") then
 
               adr_o <= X"01" & d_regs_out_i;
 
               ld_o <= "11";
 
               ld_sp_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            elsif (rdy_i = '1' and
 
                   zw_REG_OP = X"BA") then
 
               d_regs_in_o <= adr_sp_i (7 downto 0);
 
               ch_a_o <= adr_sp_i (7 downto 0);
 
               ch_b_o <= X"00";
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            elsif (rdy_i = '1') then
 
               ch_a_o <= d_regs_out_i;
 
               ch_b_o <= X"00";
 
               load_regs_o <= '1';
 
               sig_SYNC <= '1';
 
               fetch_o <= '1';
 
            end if;
 
         when RES =>
 
            ld_o <= "11";
 
            ld_pc_o <= '1';
 
            ld_sp_o <= '1';
 
         when others =>
 
            null;
 
      end case;
 
   end process output_proc;
 
 
   -- Concurrent Statements
   -- Concurrent Statements
   -- Clocked output assignments
   -- Clocked output assignments
   d_o <= d_o_cld;
   d_o <= d_o_cld;
   rd_o <= rd_o_cld;
   rd_o <= rd_o_cld;
   sync_o <= sync_o_cld;
   sync_o <= sync_o_cld;
   wr_n_o <= wr_n_o_cld;
 
   wr_o <= wr_o_cld;
   wr_o <= wr_o_cld;
END fsm;
end fsm;
 
 
 No newline at end of file
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