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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [r6502_tc.vhd] - Diff between revs 11 and 14

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Rev 11 Rev 14
Line 1... Line 1... 
-- VHDL Entity R6502_TC.R6502_TC.symbol
 
-- VHDL Entity R6502_TC.R6502_TC.symbol
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (TEST)
 
--          at - 22:53:22 04.01.2009
 
--          at - 19:21:55 07.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_arith.all;
 
USE ieee.std_logic_arith.all;
 
 
 
 
 
entity R6502_TC is
 
ENTITY R6502_TC IS
 
   port(
 
   PORT(
 
      clk_clk_i   : in     std_logic;
 
      clk_clk_i   : IN     std_logic;
 
      d_i         : in     std_logic_vector (7 downto 0);
 
      d_i         : IN     std_logic_vector (7 DOWNTO 0);
 
      irq_n_i     : in     std_logic;
 
      irq_n_i     : IN     std_logic;
 
      nmi_n_i     : in     std_logic;
 
      nmi_n_i     : IN     std_logic;
 
      rdy_i       : in     std_logic;
 
      rdy_i       : IN     std_logic;
 
      rst_rst_n_i : in     std_logic;
 
      rst_rst_n_i : IN     std_logic;
 
      so_n_i      : in     std_logic;
 
      so_n_i      : IN     std_logic;
 
      a_o         : out    std_logic_vector (15 downto 0);
 
      a_o         : OUT    std_logic_vector (15 DOWNTO 0);
 
      d_o         : out    std_logic_vector (7 downto 0);
 
      d_o         : OUT    std_logic_vector (7 DOWNTO 0);
 
      rd_o        : out    std_logic;
 
      rd_o        : OUT    std_logic;
 
      sync_o      : out    std_logic;
 
      sync_o      : OUT    std_logic;
 
      wr_n_o      : out    std_logic;
 
      wr_n_o      : OUT    std_logic;
 
      wr_o        : out    std_logic
 
      wr_o        : OUT    std_logic
 
   );
 
   );
 
 
 
 
 
-- Declarations
 
-- Declarations
 
 
 
 
 
end R6502_TC ;
 
END R6502_TC ;
 
 
 
 
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
--                                                                                                                                             
--
Line 52... Line 52... 
-- Edited:  by eda on 04 Jan 2009  
-- Edited:  by eda on 04 Jan 2009  
--
 
--
 
-- VHDL Architecture R6502_TC.R6502_TC.struct
 
-- VHDL Architecture R6502_TC.R6502_TC.struct
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (TEST)
 
--          at - 22:53:22 04.01.2009
 
--          at - 19:21:55 07.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
 
 
 
 
library R6502_TC;
 
 
 
 
 
 
 
architecture struct of R6502_TC is
 
ARCHITECTURE struct OF R6502_TC IS
 
 
 
 
 
   -- Architecture declarations
 
   -- Architecture declarations
 
 
 
 
 
   -- Internal signal declarations
 
   -- Internal signal declarations
 
 
 
 
 
 
 
 
 
   -- Component Declarations
 
   -- Component Declarations
 
   component Core
 
   COMPONENT Core
 
   port (
 
   PORT (
 
      clk_clk_i   : in     std_logic ;
 
      clk_clk_i   : IN     std_logic ;
 
      d_i         : in     std_logic_vector (7 downto 0);
 
      d_i         : IN     std_logic_vector (7 DOWNTO 0);
 
      irq_n_i     : in     std_logic ;
 
      irq_n_i     : IN     std_logic ;
 
      nmi_n_i     : in     std_logic ;
 
      nmi_n_i     : IN     std_logic ;
 
      rdy_i       : in     std_logic ;
 
      rdy_i       : IN     std_logic ;
 
      rst_rst_n_i : in     std_logic ;
 
      rst_rst_n_i : IN     std_logic ;
 
      so_n_i      : in     std_logic ;
 
      so_n_i      : IN     std_logic ;
 
      a_o         : out    std_logic_vector (15 downto 0);
 
      a_o         : OUT    std_logic_vector (15 DOWNTO 0);
 
      d_o         : out    std_logic_vector (7 downto 0);
 
      d_o         : OUT    std_logic_vector (7 DOWNTO 0);
 
      rd_o        : out    std_logic ;
 
      rd_o        : OUT    std_logic ;
 
      sync_o      : out    std_logic ;
 
      sync_o      : OUT    std_logic ;
 
      wr_n_o      : out    std_logic ;
 
      wr_n_o      : OUT    std_logic ;
 
      wr_o        : out    std_logic
 
      wr_o        : OUT    std_logic
 
   );
 
   );
 
   end component;
 
   END COMPONENT;
 
 
 
 
 
   -- Optional embedded configurations
 
 
 
   -- pragma synthesis_off
 
 
 
   for all : Core use entity R6502_TC.Core;
 
 
 
   -- pragma synthesis_on
 
 
 
 
 
 
 
 
 
BEGIN
 
begin
 
 
 
 
 
 
 
   -- Instance port mappings.
 
   -- Instance port mappings.
 
   U_0 : Core
 
   U_0 : Core
 
      port map (
 
      PORT MAP (
 
         clk_clk_i   => clk_clk_i,
 
         clk_clk_i   => clk_clk_i,
 
         d_i         => d_i,
 
         d_i         => d_i,
 
         irq_n_i     => irq_n_i,
 
         irq_n_i     => irq_n_i,
 
         nmi_n_i     => nmi_n_i,
 
         nmi_n_i     => nmi_n_i,
 
         rdy_i       => rdy_i,
 
         rdy_i       => rdy_i,
Line 114... Line 108... 
         sync_o      => sync_o,
 
         sync_o      => sync_o,
 
         wr_n_o      => wr_n_o,
 
         wr_n_o      => wr_n_o,
 
         wr_o        => wr_o
 
         wr_o        => wr_o
 
      );
 
      );
 
 
 
 
 
end struct;
 
END struct;
 
 
 
 
 
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