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-- VHDL Entity R6502_TC.R6502_TC.symbol
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-- VHDL Entity R6502_TC.R6502_TC.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (TEST)
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:21:55 07.01.2009
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-- at - 11:47:57 23.02.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY R6502_TC IS
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entity R6502_TC is
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PORT(
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port(
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clk_clk_i : IN std_logic;
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clk_clk_i : in std_logic;
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d_i : IN std_logic_vector (7 DOWNTO 0);
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d_i : in std_logic_vector (7 downto 0);
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irq_n_i : IN std_logic;
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irq_n_i : in std_logic;
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nmi_n_i : IN std_logic;
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nmi_n_i : in std_logic;
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rdy_i : IN std_logic;
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rdy_i : in std_logic;
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rst_rst_n_i : IN std_logic;
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rst_rst_n_i : in std_logic;
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so_n_i : IN std_logic;
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so_n_i : in std_logic;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
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a_o : out std_logic_vector (15 downto 0);
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d_o : OUT std_logic_vector (7 DOWNTO 0);
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d_o : out std_logic_vector (7 downto 0);
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rd_o : OUT std_logic;
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rd_o : out std_logic;
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sync_o : OUT std_logic;
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sync_o : out std_logic;
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wr_n_o : OUT std_logic;
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wr_o : out std_logic
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wr_o : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END R6502_TC ;
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end R6502_TC ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- scantara2003@yahoo.de
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
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-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- <<-- more -->>
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-- <<-- more -->>
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-- Title: Top Level
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-- Title: Top Level
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-- Path: R6502_TC/R6502_TC/struct
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-- Path: R6502_TC/R6502_TC/struct
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-- Edited: by eda on 04 Jan 2009
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-- Edited: by eda on 10 Feb 2009
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--
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--
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-- VHDL Architecture R6502_TC.R6502_TC.struct
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-- VHDL Architecture R6502_TC.R6502_TC.struct
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (TEST)
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:21:55 07.01.2009
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-- at - 11:47:58 23.02.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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library R6502_TC;
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ARCHITECTURE struct OF R6502_TC IS
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architecture struct of R6502_TC is
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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-- Component Declarations
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-- Component Declarations
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COMPONENT Core
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component Core
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PORT (
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port (
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clk_clk_i : IN std_logic ;
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clk_clk_i : in std_logic ;
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d_i : IN std_logic_vector (7 DOWNTO 0);
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d_i : in std_logic_vector (7 downto 0);
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irq_n_i : IN std_logic ;
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irq_n_i : in std_logic ;
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nmi_n_i : IN std_logic ;
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nmi_n_i : in std_logic ;
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rdy_i : IN std_logic ;
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rdy_i : in std_logic ;
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rst_rst_n_i : IN std_logic ;
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rst_rst_n_i : in std_logic ;
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so_n_i : IN std_logic ;
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so_n_i : in std_logic ;
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a_o : OUT std_logic_vector (15 DOWNTO 0);
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a_o : out std_logic_vector (15 downto 0);
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d_o : OUT std_logic_vector (7 DOWNTO 0);
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d_o : out std_logic_vector (7 downto 0);
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rd_o : OUT std_logic ;
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rd_o : out std_logic ;
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sync_o : OUT std_logic ;
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sync_o : out std_logic ;
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wr_n_o : OUT std_logic ;
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wr_o : out std_logic
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wr_o : OUT std_logic
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);
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);
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END COMPONENT;
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end component;
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-- Optional embedded configurations
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-- pragma synthesis_off
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for all : Core use entity R6502_TC.Core;
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-- pragma synthesis_on
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BEGIN
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begin
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-- Instance port mappings.
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-- Instance port mappings.
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U_0 : Core
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U_0 : Core
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PORT MAP (
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port map (
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clk_clk_i => clk_clk_i,
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clk_clk_i => clk_clk_i,
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d_i => d_i,
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d_i => d_i,
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irq_n_i => irq_n_i,
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irq_n_i => irq_n_i,
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nmi_n_i => nmi_n_i,
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nmi_n_i => nmi_n_i,
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rdy_i => rdy_i,
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rdy_i => rdy_i,
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Line 108... |
so_n_i => so_n_i,
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so_n_i => so_n_i,
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a_o => a_o,
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a_o => a_o,
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d_o => d_o,
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d_o => d_o,
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rd_o => rd_o,
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rd_o => rd_o,
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sync_o => sync_o,
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sync_o => sync_o,
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wr_n_o => wr_n_o,
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wr_o => wr_o
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wr_o => wr_o
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);
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);
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END struct;
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end struct;
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No newline at end of file
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No newline at end of file
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