| Line 1... |
Line 1... |
-- VHDL Entity R6502_TC.R6502_TC.symbol
|
-- VHDL Entity R6502_TC.R6502_TC.symbol
|
--
|
--
|
-- Created:
|
-- Created:
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
|
-- at - 19:07:11 08.04.2008
|
-- at - 19:49:04 17.04.2008
|
--
|
--
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
--
|
--
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
| Line 44... |
Line 44... |
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
|
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
|
--
|
--
|
-- CVS Revisins History
|
-- CVS Revisins History
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
--
|
|
-- Title: Top Level for the 6502 Core
|
-- Title: Top Level for the 6502 Core
|
-- Path: R6502_TC/R6502_TC/struct
|
-- Path: R6502_TC/R6502_TC/struct
|
-- Edited: by eda on 08 Apr 2008
|
-- Edited: by eda on 17 Apr 2008
|
--
|
--
|
-- VHDL Architecture R6502_TC.R6502_TC.struct
|
-- VHDL Architecture R6502_TC.R6502_TC.struct
|
--
|
--
|
-- Created:
|
-- Created:
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
|
-- at - 19:07:11 08.04.2008
|
-- at - 19:49:04 17.04.2008
|
--
|
--
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
--
|
--
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
| Line 67... |
Line 66... |
architecture struct of R6502_TC is
|
architecture struct of R6502_TC is
|
|
|
-- Architecture declarations
|
-- Architecture declarations
|
|
|
-- Internal signal declarations
|
-- Internal signal declarations
|
signal nmi_i : std_logic;
|
|
|
|
|
|
-- Component Declarations
|
-- Component Declarations
|
component Core
|
component Core
|
port (
|
port (
|
clk_clk_i : in std_logic ;
|
clk_clk_i : in std_logic ;
|
d_i : in std_logic_vector (7 downto 0);
|
d_i : in std_logic_vector (7 downto 0);
|
irq_n_i : in std_logic ;
|
irq_n_i : in std_logic ;
|
nmi_i : in std_logic ;
|
nmi_n_i : in std_logic ;
|
rdy_i : in std_logic ;
|
rdy_i : in std_logic ;
|
rst_rst_n_i : in std_logic ;
|
rst_rst_n_i : in std_logic ;
|
so_n_i : in std_logic ;
|
so_n_i : in std_logic ;
|
a_o : out std_logic_vector (15 downto 0);
|
a_o : out std_logic_vector (15 downto 0);
|
d_o : out std_logic_vector (7 downto 0);
|
d_o : out std_logic_vector (7 downto 0);
|
| Line 88... |
Line 86... |
sync_o : out std_logic ;
|
sync_o : out std_logic ;
|
wr_n_o : out std_logic ;
|
wr_n_o : out std_logic ;
|
wr_o : out std_logic
|
wr_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
component fsm_nmi
|
|
port (
|
|
clk_clk_i : in std_logic ;
|
|
nmi_n_i : in std_logic ;
|
|
rst_rst_n_i : in std_logic ;
|
|
nmi_o : out std_logic
|
|
);
|
|
end component;
|
|
|
|
-- Optional embedded configurations
|
-- Optional embedded configurations
|
-- pragma synthesis_off
|
-- pragma synthesis_off
|
for all : Core use entity R6502_TC.Core;
|
for all : Core use entity R6502_TC.Core;
|
for all : fsm_nmi use entity R6502_TC.fsm_nmi;
|
|
-- pragma synthesis_on
|
-- pragma synthesis_on
|
|
|
|
|
begin
|
begin
|
|
|
| Line 112... |
Line 101... |
U_0 : Core
|
U_0 : Core
|
port map (
|
port map (
|
clk_clk_i => clk_clk_i,
|
clk_clk_i => clk_clk_i,
|
d_i => d_i,
|
d_i => d_i,
|
irq_n_i => irq_n_i,
|
irq_n_i => irq_n_i,
|
nmi_i => nmi_i,
|
nmi_n_i => nmi_n_i,
|
rdy_i => rdy_i,
|
rdy_i => rdy_i,
|
rst_rst_n_i => rst_rst_n_i,
|
rst_rst_n_i => rst_rst_n_i,
|
so_n_i => so_n_i,
|
so_n_i => so_n_i,
|
a_o => a_o,
|
a_o => a_o,
|
d_o => d_o,
|
d_o => d_o,
|
rd_o => rd_o,
|
rd_o => rd_o,
|
sync_o => sync_o,
|
sync_o => sync_o,
|
wr_n_o => wr_n_o,
|
wr_n_o => wr_n_o,
|
wr_o => wr_o
|
wr_o => wr_o
|
);
|
);
|
U_3 : fsm_nmi
|
|
port map (
|
|
clk_clk_i => clk_clk_i,
|
|
nmi_n_i => nmi_n_i,
|
|
rst_rst_n_i => rst_rst_n_i,
|
|
nmi_o => nmi_i
|
|
);
|
|
|
|
end struct;
|
end struct;
|
|
|
No newline at end of file
|
No newline at end of file
|
