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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [reg_pc.vhd] - Diff between revs 5 and 11

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Line 1... Line 1... 
-- VHDL Entity R6502_TC.Reg_PC.symbol
 
-- VHDL Entity R6502_TC.Reg_PC.symbol
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          at - 19:48:44 17.04.2008
 
--          at - 22:53:05 04.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
Line 15... Line 15... 
      adr_i        : in     std_logic_vector (15 downto 0);
 
      adr_i        : in     std_logic_vector (15 downto 0);
 
      clk_clk_i    : in     std_logic;
 
      clk_clk_i    : in     std_logic;
 
      ld_i         : in     std_logic_vector (1 downto 0);
 
      ld_i         : in     std_logic_vector (1 downto 0);
 
      ld_pc_i      : in     std_logic;
 
      ld_pc_i      : in     std_logic;
 
      offset_i     : in     std_logic_vector (15 downto 0);
 
      offset_i     : in     std_logic_vector (15 downto 0);
 
      rst_rst_i    : in     std_logic;
 
      rst_rst_n_i  : in     std_logic;
 
      sel_pc_as_i  : in     std_logic;
 
      sel_pc_as_i  : in     std_logic;
 
      sel_pc_in_i  : in     std_logic;
 
      sel_pc_in_i  : in     std_logic;
 
      sel_pc_val_i : in     std_logic_vector (1 downto 0);
 
      sel_pc_val_i : in     std_logic_vector (1 downto 0);
 
      adr_nxt_pc_o : out    std_logic_vector (15 downto 0);
 
      adr_nxt_pc_o : out    std_logic_vector (15 downto 0);
 
      adr_pc_o     : out    std_logic_vector (15 downto 0);
 
      adr_pc_o     : out    std_logic_vector (15 downto 0)
 
      cout_pc_o    : out    std_logic
 
 
 
   );
 
   );
 
 
 
 
 
-- Declarations
 
-- Declarations
 
 
 
 
 
end Reg_PC ;
 
end Reg_PC ;
Line 43... Line 42... 
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     
--                                                                                                                                             
--                                                                                                                                             
-- CVS Revisins History                                                                                                                        
-- CVS Revisins History                                                                                                                        
--                                                                                                                                             
--                                                                                                                                             
-- $Log: not supported by cvs2svn $                                                                                                                                       
-- $Log: not supported by cvs2svn $                                                                                                                                       
 
 
--   <<-- more -->>                                                                                                                            
-- Title:  Program Counter Logic  
-- Title:  Program Counter Logic  
-- Path:  R6502_TC/Reg_PC/struct  
-- Path:  R6502_TC/Reg_PC/struct  
-- Edited:  by eda on 17 Apr 2008  
-- Edited:  by eda on 01 Jan 2009  
--
 
--
 
-- VHDL Architecture R6502_TC.Reg_PC.struct
 
-- VHDL Architecture R6502_TC.Reg_PC.struct
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          at - 19:48:44 17.04.2008
 
--          at - 22:53:06 04.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
Line 65... Line 65... 
architecture struct of Reg_PC is
 
architecture struct of Reg_PC is
 
 
 
 
 
   -- Architecture declarations
 
   -- Architecture declarations
 
 
 
 
 
   -- Internal signal declarations
 
   -- Internal signal declarations
 
   signal d        : std_logic_vector(7 downto 0);
 
   signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
 
   signal d1       : std_logic_vector(7 downto 0);
 
   signal adr_pc_low_o_i  : std_logic_vector(7 downto 0);
 
   signal dout     : std_logic;
 
   signal adr_pc_o_i      : std_logic_vector(15 downto 0);
 
   signal dout1    : std_logic_vector(7 downto 0);
 
   signal as_n_o_i        : std_logic;
 
   signal dout3    : std_logic;
 
   signal ci_o_i          : std_logic;
 
   signal dout5    : std_logic_vector(7 downto 0);
 
   signal cout_pc_o_i     : std_logic;
 
   signal dout6    : std_logic_vector(7 downto 0);
 
   signal load3_o_i       : std_logic;
 
   signal load     : std_logic;
 
   signal load_o_i        : std_logic;
 
   signal load3    : std_logic;
 
   signal offset_high_o_i : std_logic_vector(7 downto 0);
 
 
 
   signal offset_low_o_i  : std_logic_vector(7 downto 0);
 
 
 
   signal val_o_i         : std_logic_vector(7 downto 0);
 
   signal val_one  : std_logic_vector(7 downto 0);
 
   signal val_one  : std_logic_vector(7 downto 0);
 
   signal val_two  : std_logic_vector(7 downto 0);
 
 
 
   signal val_zero : std_logic_vector(7 downto 0);
 
   signal val_zero : std_logic_vector(7 downto 0);
 
 
 
 
 
   -- Implicit buffer signal declarations
 
   -- Implicit buffer signal declarations
 
   signal adr_pc_o_internal  : std_logic_vector (15 downto 0);
 
   signal adr_pc_o_internal  : std_logic_vector (15 downto 0);
 
   signal cout_pc_o_internal : std_logic;
 
   signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
 
 
 
 
 
 
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
 
 
 
   signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
 
 
 
   signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
 
 
 
   signal mw_U_11sum : unsigned(8 downto 0);
 
 
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_12' of 'addsub'
 
 
 
   signal mw_U_12temp_din0 : std_logic_vector(8 downto 0);
 
 
 
   signal mw_U_12temp_din1 : std_logic_vector(8 downto 0);
 
 
 
   signal mw_U_12sum : unsigned(8 downto 0);
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
 
   signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
   signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
 
   signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
 
   signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
 
 
 
 
 
 
 
 
 
begin
 
begin
 
   -- Architecture concurrent statements
 
 
 
   -- HDL Embedded Text Block 1 eb1
 
 
 
   -- eb1 1
 
 
 
   adr_nxt_pc_o(7 DOWNTO 0) <= d;
 
 
 
 
 
 
 
   -- HDL Embedded Text Block 2 eb2
 
 
 
   -- eb1 1
 
 
 
   val_zero (7 downto 0) <= X"00";
 
 
 
   val_one (7 downto 0) <= X"01";
 
 
 
   val_two (7 downto 0) <= X"02";
 
 
 
 
 
 
 
   -- HDL Embedded Text Block 3 eb3
 
 
 
   -- eb1 1
 
 
 
   adr_nxt_pc_o(15 DOWNTO 8) <= d1;
 
 
 
 
 
 
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
 
   u_11combo_proc: process (dout5, dout1, dout3, val_zero(0))
 
   mw_U_11temp_din0 <= '0' & adr_pc_low_o_i;
 
   variable temp_din0 : std_logic_vector(8 downto 0);
 
   mw_U_11temp_din1 <= '0' & val_o_i;
 
   variable temp_din1 : std_logic_vector(8 downto 0);
 
   u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, as_n_o_i)
 
   variable temp_sum : unsigned(8 downto 0);
 
 
 
   variable temp_carry : std_logic;
 
   variable temp_carry : std_logic;
 
   variable temp_cout : std_logic;
 
 
 
   begin
 
   begin
 
      temp_din0 := '0' & dout5;
 
      temp_carry := '0';
 
      temp_din1 := '0' & dout1;
 
      if (as_n_o_i = '1') then
 
      temp_carry := val_zero(0);
 
         mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
 
      if (dout3 = '1') then
 
 
 
         temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
 
 
 
         temp_cout := temp_sum(8) ;
 
 
 
      else
 
      else
 
         temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
 
         mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
 
         temp_cout := temp_sum(8) ;
 
 
 
      end if;
 
      end if;
 
      d <= conv_std_logic_vector(temp_sum(7 downto 0),8);
 
 
 
      cout_pc_o_internal <= temp_cout;
 
 
 
   end process u_11combo_proc;
 
   end process u_11combo_proc;
 
 
 
   adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
 
 
 
   cout_pc_o_i <= mw_U_11sum(8);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
 
   -- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
 
   u_12combo_proc: process (dout6, offset_i(15 DOWNTO 8), dout3, dout)
 
   mw_U_12temp_din0 <= '0' & adr_pc_high_o_i;
 
   variable temp_din0 : std_logic_vector(8 downto 0);
 
   mw_U_12temp_din1 <= '0' & offset_high_o_i;
 
   variable temp_din1 : std_logic_vector(8 downto 0);
 
   u_12combo_proc: process (mw_U_12temp_din0, mw_U_12temp_din1, as_n_o_i, ci_o_i)
 
   variable temp_sum : unsigned(8 downto 0);
 
 
 
   variable temp_carry : std_logic;
 
   variable temp_carry : std_logic;
 
   begin
 
   begin
 
      temp_din0 := '0' & dout6;
 
      temp_carry := ci_o_i;
 
      temp_din1 := '0' & offset_i(15 DOWNTO 8);
 
      if (as_n_o_i = '1') then
 
      temp_carry := dout;
 
         mw_U_12sum <= unsigned(mw_U_12temp_din0) + unsigned(mw_U_12temp_din1) + temp_carry;
 
      if (dout3 = '1') then
 
 
 
         temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
 
 
 
      else
 
      else
 
         temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
 
         mw_U_12sum <= unsigned(mw_U_12temp_din0) - unsigned(mw_U_12temp_din1) - temp_carry;
 
      end if;
 
      end if;
 
      d1 <= conv_std_logic_vector(temp_sum(7 downto 0),8);
 
 
 
   end process u_12combo_proc;
 
   end process u_12combo_proc;
 
 
 
   adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_12sum(7 downto 0),8);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
   adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
 
   adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
 
   u_0seq_proc: process (clk_clk_i, rst_rst_i)
 
   u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
 
   begin
 
   begin
 
      if (rst_rst_i = '1') then
 
      if (rst_rst_n_i = '0') then
 
         mw_U_0reg_cval <= "00000000";
 
         mw_U_0reg_cval <= "00000000";
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
         if (load = '1') then
 
         if (load_o_i = '1') then
 
            mw_U_0reg_cval <= d;
 
            mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
 
         end if;
 
         end if;
 
      end if;
 
      end if;
 
   end process u_0seq_proc;
 
   end process u_0seq_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
 
   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
 
   adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
 
   adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
 
   u_4seq_proc: process (clk_clk_i, rst_rst_i)
 
   u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
 
   begin
 
   begin
 
      if (rst_rst_i = '1') then
 
      if (rst_rst_n_i = '0') then
 
         mw_U_4reg_cval <= "00000000";
 
         mw_U_4reg_cval <= "00000000";
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
         if (load3 = '1') then
 
         if (load3_o_i = '1') then
 
            mw_U_4reg_cval <= d1;
 
            mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
 
         end if;
 
         end if;
 
      end if;
 
      end if;
 
   end process u_4seq_proc;
 
   end process u_4seq_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
 
   load <= ld_pc_i and ld_i(0);
 
   load_o_i <= ld_pc_i and ld_i(0);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'
 
   load3 <= ld_pc_i and ld_i(1);
 
   load3_o_i <= ld_pc_i and ld_i(1);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_10' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_10' of 'and'
 
   dout <= cout_pc_o_internal and ld_pc_i;
 
   ci_o_i <= cout_pc_o_i and ld_pc_i;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
 
   -- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
 
   dout3 <= not(sel_pc_as_i);
 
   val_zero <= "00000000";
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_5' of 'mux'
 
   -- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
 
   u_5combo_proc: process(val_one, val_two, offset_i(7 DOWNTO 0),
 
   val_one <= "00000001";
 
                          val_zero, sel_pc_val_i)
 
 
 
   begin
 
   -- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
 
      case sel_pc_val_i is
 
   as_n_o_i <= not(sel_pc_as_i);
 
      when "00" => dout1 <= val_one;
 
 
 
      when "01" => dout1 <= val_two;
 
 
 
      when "10" => dout1 <= offset_i(7 DOWNTO 0);
 
 
 
      when "11" => dout1 <= val_zero;
 
 
 
      when others => dout1 <= (others => 'X');
 
 
 
      end case;
 
 
 
   end process u_5combo_proc;
 
 
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
   u_8combo_proc: process(adr_pc_o_internal(7 DOWNTO 0),
 
   u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
 
                          adr_i(7 DOWNTO 0), sel_pc_in_i)
 
 
 
   begin
 
   begin
 
      case sel_pc_in_i is
 
      case sel_pc_in_i is
 
      when '0' => dout5 <= adr_pc_o_internal(7 DOWNTO 0);
 
      when '0' => adr_pc_o_i <= adr_pc_o_internal;
 
      when '1' => dout5 <= adr_i(7 DOWNTO 0);
 
      when '1' => adr_pc_o_i <= adr_i;
 
      when others => dout5 <= (others => 'X');
 
      when others => adr_pc_o_i <= (others => 'X');
 
      end case;
 
      end case;
 
   end process u_8combo_proc;
 
   end process u_8combo_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_9' of 'mux'
 
   -- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
 
   u_9combo_proc: process(adr_pc_o_internal(15 DOWNTO 8),
 
   u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
 
                          adr_i(15 DOWNTO 8), sel_pc_in_i)
 
                           sel_pc_val_i)
 
   begin
 
   begin
 
      case sel_pc_in_i is
 
      case sel_pc_val_i is
 
      when '0' => dout6 <= adr_pc_o_internal(15 DOWNTO 8);
 
      when "00" => val_o_i <= val_one;
 
      when '1' => dout6 <= adr_i(15 DOWNTO 8);
 
      when "01" => val_o_i <= val_zero;
 
      when others => dout6 <= (others => 'X');
 
      when "10" => val_o_i <= offset_low_o_i;
 
 
 
      when "11" => val_o_i <= val_zero;
 
 
 
      when others => val_o_i <= (others => 'X');
 
      end case;
 
      end case;
 
   end process u_9combo_proc;
 
   end process u_13combo_proc;
 
 
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_3' of 'split'
 
 
 
   adr_pc_low_o_i <= adr_pc_o_i(7 downto 0);
 
 
 
   adr_pc_high_o_i <= adr_pc_o_i(15 downto 8);
 
 
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_5' of 'split'
 
 
 
   offset_low_o_i <= offset_i(7 downto 0);
 
 
 
   offset_high_o_i <= offset_i(15 downto 8);
 
 
 
 
 
   -- Instance port mappings.
 
   -- Instance port mappings.
 
 
 
 
 
   -- Implicit buffered output assignments
 
   -- Implicit buffered output assignments
 
   adr_pc_o  <= adr_pc_o_internal;
 
   adr_pc_o  <= adr_pc_o_internal;
 
   cout_pc_o <= cout_pc_o_internal;
 
   adr_nxt_pc_o <= adr_nxt_pc_o_internal;
 
 
 
 
 
end struct;
 
end struct;
 
 
 
 
 
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