Line 1... |
Line 1... |
-- VHDL Entity R6502_TC.Reg_PC.symbol
|
-- VHDL Entity R6502_TC.Reg_PC.symbol
|
--
|
--
|
-- Created:
|
-- Created:
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
|
-- by - eda.UNKNOWN (TEST)
|
-- at - 22:53:05 04.01.2009
|
-- at - 19:07:21 07.01.2009
|
--
|
--
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
--
|
--
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_arith.all;
|
USE ieee.std_logic_arith.all;
|
|
|
entity Reg_PC is
|
ENTITY Reg_PC IS
|
port(
|
PORT(
|
adr_i : in std_logic_vector (15 downto 0);
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adr_i : IN std_logic_vector (15 DOWNTO 0);
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clk_clk_i : in std_logic;
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clk_clk_i : IN std_logic;
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ld_i : in std_logic_vector (1 downto 0);
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ld_i : IN std_logic_vector (1 DOWNTO 0);
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ld_pc_i : in std_logic;
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ld_pc_i : IN std_logic;
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offset_i : in std_logic_vector (15 downto 0);
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offset_i : IN std_logic_vector (15 DOWNTO 0);
|
rst_rst_n_i : in std_logic;
|
rst_rst_n_i : IN std_logic;
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sel_pc_as_i : in std_logic;
|
sel_pc_in_i : IN std_logic;
|
sel_pc_in_i : in std_logic;
|
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
|
sel_pc_val_i : in std_logic_vector (1 downto 0);
|
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
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adr_nxt_pc_o : out std_logic_vector (15 downto 0);
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adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
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adr_pc_o : out std_logic_vector (15 downto 0)
|
|
);
|
);
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-- Declarations
|
-- Declarations
|
|
|
end Reg_PC ;
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END Reg_PC ;
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|
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-- Jens-D. Gutschmidt Project: R6502_TC
|
-- Jens-D. Gutschmidt Project: R6502_TC
|
-- scantara2003@yahoo.de
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
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-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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Line 45... |
Line 44... |
--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
-- <<-- more -->>
|
-- <<-- more -->>
|
-- Title: Program Counter Logic
|
-- Title: Program Counter Logic
|
-- Path: R6502_TC/Reg_PC/struct
|
-- Path: R6502_TC/Reg_PC/struct
|
-- Edited: by eda on 01 Jan 2009
|
-- Edited: by eda on 07 Jan 2009
|
--
|
--
|
-- VHDL Architecture R6502_TC.Reg_PC.struct
|
-- VHDL Architecture R6502_TC.Reg_PC.struct
|
--
|
--
|
-- Created:
|
-- Created:
|
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
|
-- by - eda.UNKNOWN (TEST)
|
-- at - 22:53:06 04.01.2009
|
-- at - 19:07:21 07.01.2009
|
--
|
--
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
|
--
|
--
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_arith.all;
|
USE ieee.std_logic_arith.all;
|
|
|
|
|
architecture struct of Reg_PC is
|
ARCHITECTURE struct OF Reg_PC IS
|
|
|
-- Architecture declarations
|
-- Architecture declarations
|
|
|
-- Internal signal declarations
|
-- Internal signal declarations
|
signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
|
SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0);
|
signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
|
SIGNAL adr_pc_low_o_i : std_logic_vector(7 DOWNTO 0);
|
signal adr_pc_o_i : std_logic_vector(15 downto 0);
|
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
|
signal as_n_o_i : std_logic;
|
SIGNAL ci_o_i : std_logic;
|
signal ci_o_i : std_logic;
|
SIGNAL cout_pc_o_i : std_logic;
|
signal cout_pc_o_i : std_logic;
|
SIGNAL load3_o_i : std_logic;
|
signal load3_o_i : std_logic;
|
SIGNAL load_o_i : std_logic;
|
signal load_o_i : std_logic;
|
SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0);
|
signal offset_high_o_i : std_logic_vector(7 downto 0);
|
SIGNAL offset_low_o_i : std_logic_vector(7 DOWNTO 0);
|
signal offset_low_o_i : std_logic_vector(7 downto 0);
|
SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
|
signal val_o_i : std_logic_vector(7 downto 0);
|
SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
|
signal val_one : std_logic_vector(7 downto 0);
|
SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
|
signal val_zero : std_logic_vector(7 downto 0);
|
|
|
|
-- Implicit buffer signal declarations
|
-- Implicit buffer signal declarations
|
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
|
SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
|
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
|
SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
|
|
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
|
|
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
|
|
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
|
|
signal mw_U_11sum : unsigned(8 downto 0);
|
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_12' of 'addsub'
|
|
signal mw_U_12temp_din0 : std_logic_vector(8 downto 0);
|
|
signal mw_U_12temp_din1 : std_logic_vector(8 downto 0);
|
|
signal mw_U_12sum : unsigned(8 downto 0);
|
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
|
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
|
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
|
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
|
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
|
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
|
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
|
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'
|
|
SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0);
|
|
|
|
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'
|
|
SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0);
|
|
|
begin
|
|
|
|
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
|
BEGIN
|
mw_U_11temp_din0 <= '0' & adr_pc_low_o_i;
|
|
mw_U_11temp_din1 <= '0' & val_o_i;
|
-- ModuleWare code(v1.9) for instance 'U_2' of 'add'
|
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, as_n_o_i)
|
u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i)
|
variable temp_carry : std_logic;
|
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
|
begin
|
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
|
|
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
|
|
VARIABLE temp_carry : std_logic;
|
|
BEGIN
|
|
temp_din0 := '0' & adr_pc_low_o_i;
|
|
temp_din1 := '0' & val_o_i;
|
temp_carry := '0';
|
temp_carry := '0';
|
if (as_n_o_i = '1') then
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
|
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
|
else
|
cout_pc_o_i <= temp_sum(8) ;
|
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
|
END PROCESS u_2combo_proc;
|
end if;
|
|
end process u_11combo_proc;
|
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
|
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
|
u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
|
cout_pc_o_i <= mw_U_11sum(8);
|
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
|
|
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
|
-- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
|
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
|
mw_U_12temp_din0 <= '0' & adr_pc_high_o_i;
|
VARIABLE temp_carry : std_logic;
|
mw_U_12temp_din1 <= '0' & offset_high_o_i;
|
BEGIN
|
u_12combo_proc: process (mw_U_12temp_din0, mw_U_12temp_din1, as_n_o_i, ci_o_i)
|
temp_din0 := '0' & adr_pc_high_o_i;
|
variable temp_carry : std_logic;
|
temp_din1 := '0' & offset_high_o_i;
|
begin
|
|
temp_carry := ci_o_i;
|
temp_carry := ci_o_i;
|
if (as_n_o_i = '1') then
|
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
|
mw_U_12sum <= unsigned(mw_U_12temp_din0) + unsigned(mw_U_12temp_din1) + temp_carry;
|
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
|
else
|
END PROCESS u_11combo_proc;
|
mw_U_12sum <= unsigned(mw_U_12temp_din0) - unsigned(mw_U_12temp_din1) - temp_carry;
|
|
end if;
|
|
end process u_12combo_proc;
|
|
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_12sum(7 downto 0),8);
|
|
|
|
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
|
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
|
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
|
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
|
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
|
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
|
begin
|
BEGIN
|
if (rst_rst_n_i = '0') then
|
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
|
mw_U_0reg_cval <= "00000000";
|
mw_U_0reg_cval <= "00000000";
|
elsif (clk_clk_i'event and clk_clk_i='1') then
|
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
|
if (load_o_i = '1') then
|
IF (load_o_i = '1' OR load_o_i = 'H') THEN
|
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
|
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process u_0seq_proc;
|
END PROCESS u_0seq_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
|
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
|
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
|
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
|
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
|
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
|
begin
|
BEGIN
|
if (rst_rst_n_i = '0') then
|
IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
|
mw_U_4reg_cval <= "00000000";
|
mw_U_4reg_cval <= "00000000";
|
elsif (clk_clk_i'event and clk_clk_i='1') then
|
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
|
if (load3_o_i = '1') then
|
IF (load3_o_i = '1' OR load3_o_i = 'H') THEN
|
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
|
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process u_4seq_proc;
|
END PROCESS u_4seq_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
|
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
|
load_o_i <= ld_pc_i and ld_i(0);
|
load_o_i <= ld_pc_i AND ld_i(0);
|
|
|
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
|
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
|
load3_o_i <= ld_pc_i and ld_i(1);
|
load3_o_i <= ld_pc_i AND ld_i(1);
|
|
|
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
|
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
|
ci_o_i <= cout_pc_o_i and ld_pc_i;
|
ci_o_i <= cout_pc_o_i AND ld_pc_i;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
|
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
|
val_zero <= "00000000";
|
val_zero <= "00000000";
|
|
|
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
|
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
|
val_one <= "00000001";
|
val_one <= "00000001";
|
|
|
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
|
|
as_n_o_i <= not(sel_pc_as_i);
|
|
|
|
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
|
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
|
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
|
u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
|
begin
|
BEGIN
|
case sel_pc_in_i is
|
CASE sel_pc_in_i IS
|
when '0' => adr_pc_o_i <= adr_pc_o_internal;
|
WHEN '0'|'L' => adr_pc_o_i <= adr_pc_o_internal;
|
when '1' => adr_pc_o_i <= adr_i;
|
WHEN '1'|'H' => adr_pc_o_i <= adr_i;
|
when others => adr_pc_o_i <= (others => 'X');
|
WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
|
end case;
|
END CASE;
|
end process u_8combo_proc;
|
END PROCESS u_8combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
|
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
|
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
|
u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
|
sel_pc_val_i)
|
sel_pc_val_i)
|
begin
|
BEGIN
|
case sel_pc_val_i is
|
CASE sel_pc_val_i IS
|
when "00" => val_o_i <= val_one;
|
WHEN "00"|"L0"|"0L"|"LL" => val_o_i <= val_one;
|
when "01" => val_o_i <= val_zero;
|
WHEN "01"|"L1"|"0H"|"LH" => val_o_i <= val_zero;
|
when "10" => val_o_i <= offset_low_o_i;
|
WHEN "10"|"H0"|"1L"|"HL" => val_o_i <= offset_low_o_i;
|
when "11" => val_o_i <= val_zero;
|
WHEN "11"|"H1"|"1H"|"HH" => val_o_i <= val_zero;
|
when others => val_o_i <= (others => 'X');
|
WHEN OTHERS => val_o_i <= (OTHERS => 'X');
|
end case;
|
END CASE;
|
end process u_13combo_proc;
|
END PROCESS u_13combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
|
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
|
adr_pc_low_o_i <= adr_pc_o_i(7 downto 0);
|
mw_U_3temp_din <= adr_pc_o_i;
|
adr_pc_high_o_i <= adr_pc_o_i(15 downto 8);
|
u_3combo_proc: PROCESS (mw_U_3temp_din)
|
|
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
|
|
BEGIN
|
|
temp_din := mw_U_3temp_din(15 DOWNTO 0);
|
|
adr_pc_low_o_i <= temp_din(7 DOWNTO 0);
|
|
adr_pc_high_o_i <= temp_din(15 DOWNTO 8);
|
|
END PROCESS u_3combo_proc;
|
|
|
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
|
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
|
offset_low_o_i <= offset_i(7 downto 0);
|
mw_U_5temp_din <= offset_i;
|
offset_high_o_i <= offset_i(15 downto 8);
|
u_5combo_proc: PROCESS (mw_U_5temp_din)
|
|
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
|
|
BEGIN
|
|
temp_din := mw_U_5temp_din(15 DOWNTO 0);
|
|
offset_low_o_i <= temp_din(7 DOWNTO 0);
|
|
offset_high_o_i <= temp_din(15 DOWNTO 8);
|
|
END PROCESS u_5combo_proc;
|
|
|
-- Instance port mappings.
|
-- Instance port mappings.
|
|
|
-- Implicit buffered output assignments
|
-- Implicit buffered output assignments
|
adr_pc_o <= adr_pc_o_internal;
|
adr_pc_o <= adr_pc_o_internal;
|
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
|
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
|
|
|
end struct;
|
END struct;
|
|
|
No newline at end of file
|
No newline at end of file
|