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-- VHDL Entity R6502_TC.Reg_PC.symbol
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-- VHDL Entity R6502_TC.Reg_PC.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (TEST)
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-- by - eda.UNKNOWN (ENTW1)
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-- at - 19:25:31 10.02.2009
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-- at - 18:39:48 08.02.2010
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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END Reg_PC ;
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END Reg_PC ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- scantara2003@yahoo.de
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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--
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- CVS Revisins History
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-- CVS Revisins History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: struct.bd,v $
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-- <<-- more -->>
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-- <<-- more -->>
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-- Title: Program Counter Logic
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-- Title: Program Counter Logic
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-- Path: R6502_TC/Reg_PC/struct
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-- Path: R6502_TC/Reg_PC/struct
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-- Edited: by eda on 10 Feb 2009
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-- Edited: by eda on 08 Feb 2010
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--
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--
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-- VHDL Architecture R6502_TC.Reg_PC.struct
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-- VHDL Architecture R6502_TC.Reg_PC.struct
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (TEST)
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-- by - eda.UNKNOWN (ENTW1)
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-- at - 19:25:32 10.02.2009
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-- at - 18:39:49 08.02.2010
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
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SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
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SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
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SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
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SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
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SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
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-- Implicit buffer signal declarations
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-- Implicit buffer signal declarations
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SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
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SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
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SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
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SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
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-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
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SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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BEGIN
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BEGIN
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IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
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IF (rst_rst_n_i = '0') THEN
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mw_U_0reg_cval <= "00000000";
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mw_U_0reg_cval <= "00000000";
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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IF (load_o_i = '1' OR load_o_i = 'H') THEN
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IF (load_o_i = '1') THEN
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mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
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mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS u_0seq_proc;
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END PROCESS u_0seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
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-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
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adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
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adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
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u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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BEGIN
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BEGIN
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IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
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IF (rst_rst_n_i = '0') THEN
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mw_U_4reg_cval <= "00000000";
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mw_U_4reg_cval <= "00000000";
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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IF (load3_o_i = '1' OR load3_o_i = 'H') THEN
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IF (load3_o_i = '1') THEN
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mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
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mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS u_4seq_proc;
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END PROCESS u_4seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
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-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
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u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
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u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
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BEGIN
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BEGIN
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CASE sel_pc_in_i IS
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CASE sel_pc_in_i IS
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WHEN '0'|'L' => adr_pc_o_i <= adr_pc_o_internal;
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WHEN '0' => adr_pc_o_i <= adr_pc_o_internal;
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WHEN '1'|'H' => adr_pc_o_i <= adr_i;
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WHEN '1' => adr_pc_o_i <= adr_i;
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WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
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WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
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END CASE;
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END CASE;
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END PROCESS u_8combo_proc;
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END PROCESS u_8combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
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-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
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u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
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u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
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sel_pc_val_i)
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sel_pc_val_i)
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BEGIN
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BEGIN
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CASE sel_pc_val_i IS
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CASE sel_pc_val_i IS
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WHEN "00"|"L0"|"0L"|"LL" => val_o_i <= val_one;
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WHEN "00" => val_o_i <= val_one;
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WHEN "01"|"L1"|"0H"|"LH" => val_o_i <= val_zero;
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WHEN "01" => val_o_i <= val_zero;
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WHEN "10"|"H0"|"1L"|"HL" => val_o_i <= offset_low_o_i;
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WHEN "10" => val_o_i <= offset_low_o_i;
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WHEN "11"|"H1"|"1H"|"HH" => val_o_i <= val_zero;
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WHEN "11" => val_o_i <= val_zero;
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WHEN OTHERS => val_o_i <= (OTHERS => 'X');
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WHEN OTHERS => val_o_i <= (OTHERS => 'X');
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END CASE;
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END CASE;
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END PROCESS u_13combo_proc;
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END PROCESS u_13combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
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-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
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END PROCESS u_5combo_proc;
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END PROCESS u_5combo_proc;
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-- Instance port mappings.
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-- Instance port mappings.
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-- Implicit buffered output assignments
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-- Implicit buffered output assignments
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adr_pc_o <= adr_pc_o_internal;
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adr_nxt_pc_o <= adr_nxt_pc_o_internal;
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adr_nxt_pc_o <= adr_nxt_pc_o_internal;
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adr_pc_o <= adr_pc_o_internal;
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END struct;
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END struct;
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