Subversion Repositories cpu6502_true_cycle

-- VHDL Entity R6502_TC.Reg_PC.symbol

-- VHDL Entity R6502_TC.Reg_PC.symbol

--

--

-- Created:

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

--

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_1164.all;

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

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--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

-- CVS Revisins History                                                                                                                        

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-- $Log: not supported by cvs2svn $                                                                                                                                       

-- $Log: not supported by cvs2svn $                                                                                                                                       

-- Title:  Program Counter Logic  

-- Title:  Program Counter Logic  

-- Path:  R6502_TC/Reg_PC/struct  

-- Path:  R6502_TC/Reg_PC/struct  

--

--

-- VHDL Architecture R6502_TC.Reg_PC.struct

-- VHDL Architecture R6502_TC.Reg_PC.struct

--

--

-- Created:

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

--

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_1164.all;