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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [reg_sp.vhd] - Diff between revs 11 and 14

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Line 1... Line 1... 
-- VHDL Entity R6502_TC.Reg_SP.symbol
 
-- VHDL Entity R6502_TC.Reg_SP.symbol
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (TEST)
 
--          at - 22:53:06 04.01.2009
 
--          at - 18:23:46 07.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_arith.all;
 
USE ieee.std_logic_arith.all;
 
 
 
 
 
entity Reg_SP is
 
ENTITY Reg_SP IS
 
   port(
 
   PORT(
 
      adr_low_i   : in     std_logic_vector (7 downto 0);
 
      adr_low_i   : IN     std_logic_vector (7 DOWNTO 0);
 
      clk_clk_i   : in     std_logic;
 
      clk_clk_i   : IN     std_logic;
 
      ld_low_i    : in     std_logic;
 
      ld_low_i    : IN     std_logic;
 
      ld_sp_i     : in     std_logic;
 
      ld_sp_i     : IN     std_logic;
 
      rst_rst_n_i : in     std_logic;
 
      rst_rst_n_i : IN     std_logic;
 
      sel_sp_as_i : in     std_logic;
 
      sel_sp_as_i : IN     std_logic;
 
      sel_sp_in_i : in     std_logic;
 
      sel_sp_in_i : IN     std_logic;
 
      adr_sp_o    : out    std_logic_vector (15 downto 0)
 
      adr_sp_o    : OUT    std_logic_vector (15 DOWNTO 0)
 
   );
 
   );
 
 
 
 
 
-- Declarations
 
-- Declarations
 
 
 
 
 
end Reg_SP ;
 
END Reg_SP ;
 
 
 
 
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
--                                                                                                                                             
--
Line 47... Line 47... 
-- Edited:  by eda on 01 Jan 2009  
-- Edited:  by eda on 01 Jan 2009  
--
 
--
 
-- VHDL Architecture R6502_TC.Reg_SP.struct
 
-- VHDL Architecture R6502_TC.Reg_SP.struct
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (TEST)
 
--          at - 22:53:06 04.01.2009
 
--          at - 18:23:46 07.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_arith.all;
 
USE ieee.std_logic_arith.all;
 
 
 
 
 
 
 
 
 
architecture struct of Reg_SP is
 
ARCHITECTURE struct OF Reg_SP IS
 
 
 
 
 
   -- Architecture declarations
 
   -- Architecture declarations
 
 
 
 
 
   -- Internal signal declarations
 
   -- Internal signal declarations
 
   signal adr_sp_low_o_i  : std_logic_vector(7 downto 0);
 
   SIGNAL adr_sp_low_o_i  : std_logic_vector(7 DOWNTO 0);
 
   signal load_o_i        : std_logic;
 
   SIGNAL load_o_i        : std_logic;
 
   signal result_low1_o_i : std_logic_vector(7 downto 0);
 
   SIGNAL result_low1_o_i : std_logic_vector(7 DOWNTO 0);
 
   signal result_low_o_i  : std_logic_vector(7 downto 0);
 
   SIGNAL result_low_o_i  : std_logic_vector(7 DOWNTO 0);
 
   signal sp_as_n_o_i     : std_logic;
 
   SIGNAL sp_as_n_o_i     : std_logic;
 
   signal val_one         : std_logic_vector(7 downto 0);
 
   SIGNAL val_one         : std_logic_vector(7 DOWNTO 0);
 
 
 
 
 
   -- Implicit buffer signal declarations
 
   -- Implicit buffer signal declarations
 
   signal adr_sp_o_internal : std_logic_vector (15 downto 0);
 
   SIGNAL adr_sp_o_internal : std_logic_vector (15 DOWNTO 0);
 
 
 
 
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
 
 
 
   signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
 
 
 
   signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
 
 
 
   signal mw_U_11sum : unsigned(8 downto 0);
 
 
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
 
   signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
   SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
 
 
 
 
 
 
 
begin
 
BEGIN
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
 
   mw_U_11temp_din0 <= '0' & adr_sp_low_o_i;
 
   u_11combo_proc: PROCESS (adr_sp_low_o_i, val_one, sp_as_n_o_i)
 
   mw_U_11temp_din1 <= '0' & val_one;
 
   VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
 
   u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, sp_as_n_o_i)
 
   VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
 
   variable temp_carry : std_logic;
 
   VARIABLE temp_sum : unsigned(8 DOWNTO 0);
 
   begin
 
   VARIABLE temp_carry : std_logic;
 
 
 
   BEGIN
 
 
 
      temp_din0 := '0' & adr_sp_low_o_i;
 
 
 
      temp_din1 := '0' & val_one;
 
      temp_carry := '0';
 
      temp_carry := '0';
 
      if (sp_as_n_o_i = '1') then
 
      IF (sp_as_n_o_i = '1' OR sp_as_n_o_i = 'H') THEN
 
         mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
 
         temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
 
      else
 
      ELSE
 
         mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
 
         temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
 
      end if;
 
      END IF;
 
   end process u_11combo_proc;
 
      result_low_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
 
   result_low_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
 
   END PROCESS u_11combo_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
   adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
 
   adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
 
   u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
 
   u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
 
   begin
 
   BEGIN
 
      if (rst_rst_n_i = '0') then
 
      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
 
         mw_U_0reg_cval <= "00000000";
 
         mw_U_0reg_cval <= "00000000";
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
 
         if (load_o_i = '1') then
 
         IF (load_o_i = '1' OR load_o_i = 'H') THEN
 
            mw_U_0reg_cval <= result_low1_o_i;
 
            mw_U_0reg_cval <= result_low1_o_i;
 
         end if;
 
         END IF;
 
      end if;
 
      END IF;
 
   end process u_0seq_proc;
 
   END PROCESS u_0seq_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
 
   load_o_i <= ld_sp_i and ld_low_i;
 
   load_o_i <= ld_sp_i AND ld_low_i;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_3' of 'buff'
 
   -- ModuleWare code(v1.9) for instance 'U_3' of 'buff'
 
   adr_sp_o_internal(15 DOWNTO 8) <= val_one;
 
   adr_sp_o_internal(15 DOWNTO 8) <= val_one;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_4' of 'constval'
 
   -- ModuleWare code(v1.9) for instance 'U_4' of 'constval'
 
   val_one <= "00000001";
 
   val_one <= "00000001";
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
 
   -- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
 
   sp_as_n_o_i <= not(sel_sp_as_i);
 
   sp_as_n_o_i <= NOT(sel_sp_as_i);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
 
   u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
 
   u_8combo_proc: PROCESS(result_low_o_i, adr_low_i, sel_sp_in_i)
 
   begin
 
   BEGIN
 
      case sel_sp_in_i is
 
      CASE sel_sp_in_i IS
 
      when '0' => result_low1_o_i <= result_low_o_i;
 
      WHEN '0'|'L' => result_low1_o_i <= result_low_o_i;
 
      when '1' => result_low1_o_i <= adr_low_i;
 
      WHEN '1'|'H' => result_low1_o_i <= adr_low_i;
 
      when others => result_low1_o_i <= (others => 'X');
 
      WHEN OTHERS => result_low1_o_i <= (OTHERS => 'X');
 
      end case;
 
      END CASE;
 
   end process u_8combo_proc;
 
   END PROCESS u_8combo_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
 
   -- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
 
   adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
 
   adr_sp_low_o_i <= adr_sp_o_internal(7 DOWNTO 0);
 
 
 
 
 
   -- Instance port mappings.
 
   -- Instance port mappings.
 
 
 
 
 
   -- Implicit buffered output assignments
 
   -- Implicit buffered output assignments
 
   adr_sp_o <= adr_sp_o_internal;
 
   adr_sp_o <= adr_sp_o_internal;
 
 
 
 
 
end struct;
 
END struct;
 
 
 
 
 
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