Subversion Repositories cpu6502_true_cycle

-- VHDL Entity R6502_TC.Reg_SP.symbol

-- VHDL Entity R6502_TC.Reg_SP.symbol

--

--

-- Created:

-- Created:

--          by - eda.UNKNOWN (TEST)

--          by - eda.UNKNOWN (TEST)

--

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

--

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_1164.all;

END Reg_SP ;

END Reg_SP ;

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- scantara2003@yahoo.de                      

-- scantara2003@yahoo.de                      

--                                                                                                                                             

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

--                                                                                                                                             

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                         

-- $Log: not supported by cvs2svn $                                                                                                                         

--   <<-- more -->>                                                                                                                            

--   <<-- more -->>                                                                                                                            

-- Title:  Stack Pointer Logic  

-- Title:  Stack Pointer Logic  

-- Path:  R6502_TC/Reg_SP/struct  

-- Path:  R6502_TC/Reg_SP/struct  

--

--

-- VHDL Architecture R6502_TC.Reg_SP.struct

-- VHDL Architecture R6502_TC.Reg_SP.struct

--

--

-- Created:

-- Created:

--          by - eda.UNKNOWN (TEST)

--          by - eda.UNKNOWN (TEST)

--

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

--

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_1164.all;