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-- VHDL Entity R6502_TC.Reg_SP.symbol
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-- VHDL Entity R6502_TC.Reg_SP.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (TEST)
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-- by - eda.UNKNOWN (ENTW1)
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-- at - 19:25:32 10.02.2009
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-- at - 14:13:51 08.03.2010
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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END Reg_SP ;
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END Reg_SP ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- scantara2003@yahoo.de
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG
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-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
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--
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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--
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- CVS Revisins History
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-- CVS Revisins History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: struct.bd,v $
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-- <<-- more -->>
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-- <<-- more -->>
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-- Title: Stack Pointer Logic
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-- Title: Stack Pointer Logic
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-- Path: R6502_TC/Reg_SP/struct
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-- Path: R6502_TC/Reg_SP/struct
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-- Edited: by eda on 10 Feb 2009
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-- Edited: by eda on 21 Feb 2010
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--
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--
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-- VHDL Architecture R6502_TC.Reg_SP.struct
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-- VHDL Architecture R6502_TC.Reg_SP.struct
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (TEST)
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-- by - eda.UNKNOWN (ENTW1)
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-- at - 19:25:32 10.02.2009
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-- at - 14:13:52 08.03.2010
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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VARIABLE temp_carry : std_logic;
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VARIABLE temp_carry : std_logic;
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BEGIN
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BEGIN
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temp_din0 := '0' & adr_sp_low_o_i;
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temp_din0 := '0' & adr_sp_low_o_i;
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temp_din1 := '0' & val_one;
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temp_din1 := '0' & val_one;
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temp_carry := '0';
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temp_carry := '0';
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IF (sp_as_n_o_i = '1' OR sp_as_n_o_i = 'H') THEN
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IF (sp_as_n_o_i = '1') THEN
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temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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ELSE
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ELSE
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temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
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temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
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END IF;
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END IF;
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result_low_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
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result_low_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
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BEGIN
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BEGIN
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IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
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IF (rst_rst_n_i = '0') THEN
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mw_U_0reg_cval <= "00000000";
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mw_U_0reg_cval <= "00000000";
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
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IF (load_o_i = '1' OR load_o_i = 'H') THEN
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IF (load_o_i = '1') THEN
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mw_U_0reg_cval <= result_low1_o_i;
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mw_U_0reg_cval <= result_low1_o_i;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS u_0seq_proc;
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END PROCESS u_0seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
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-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
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u_8combo_proc: PROCESS(result_low_o_i, adr_low_i, sel_sp_in_i)
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u_8combo_proc: PROCESS(result_low_o_i, adr_low_i, sel_sp_in_i)
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BEGIN
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BEGIN
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CASE sel_sp_in_i IS
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CASE sel_sp_in_i IS
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WHEN '0'|'L' => result_low1_o_i <= result_low_o_i;
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WHEN '0' => result_low1_o_i <= result_low_o_i;
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WHEN '1'|'H' => result_low1_o_i <= adr_low_i;
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WHEN '1' => result_low1_o_i <= adr_low_i;
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WHEN OTHERS => result_low1_o_i <= (OTHERS => 'X');
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WHEN OTHERS => result_low1_o_i <= (OTHERS => 'X');
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END CASE;
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END CASE;
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END PROCESS u_8combo_proc;
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END PROCESS u_8combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
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-- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
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