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-- VHDL Entity R6502_TC.RegBank_AXY.symbol
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-- VHDL Entity R6502_TC.RegBank_AXY.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:48:45 17.04.2008
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-- at - 22:53:06 04.01.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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entity RegBank_AXY is
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entity RegBank_AXY is
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port(
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port(
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clk_clk_i : in std_logic;
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clk_clk_i : in std_logic;
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d_regs_in_i : in std_logic_vector (7 downto 0);
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d_regs_in_i : in std_logic_vector (7 downto 0);
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load_regs_i : in std_logic;
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load_regs_i : in std_logic;
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rst_rst_i : in std_logic;
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rst_rst_n_i : in std_logic;
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sel_rb_in_i : in std_logic_vector (2 downto 0);
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sel_rb_in_i : in std_logic_vector (1 downto 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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d_regs_out_o : out std_logic_vector (7 downto 0);
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d_regs_out_o : out std_logic_vector (7 downto 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_x_o : out std_logic_vector (7 downto 0);
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q_x_o : out std_logic_vector (7 downto 0);
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- CVS Revisins History
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-- CVS Revisins History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- <<-- more -->>
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-- Title: Register Bank for register A, X and Y
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-- Title: Register Bank for register A, X and Y
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-- Path: R6502_TC/RegBank_AXY/struct
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-- Path: R6502_TC/RegBank_AXY/struct
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-- Edited: by eda on 17 Apr 2008
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-- Edited: by eda on 02 Jan 2009
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--
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--
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-- VHDL Architecture R6502_TC.RegBank_AXY.struct
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-- VHDL Architecture R6502_TC.RegBank_AXY.struct
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--
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--
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-- Created:
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:48:45 17.04.2008
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-- at - 22:53:07 04.01.2009
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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architecture struct of RegBank_AXY is
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architecture struct of RegBank_AXY is
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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signal dout : std_logic_vector(7 downto 0);
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signal ld : std_logic_vector(2 downto 0);
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signal dout1 : std_logic_vector(7 downto 0);
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signal load1_o_i : std_logic;
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signal ld : std_logic_vector(3 downto 0);
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signal load2_o_i : std_logic;
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signal load : std_logic;
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signal load_o_i : std_logic;
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signal load1 : std_logic;
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signal q_mux_o_i : std_logic_vector(7 downto 0);
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signal load2 : std_logic;
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signal load3 : std_logic;
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signal q_zw : std_logic_vector(7 downto 0);
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signal val_zero : std_logic_vector(7 downto 0);
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signal val_zero : std_logic_vector(7 downto 0);
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-- Implicit buffer signal declarations
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-- Implicit buffer signal declarations
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signal q_a_o_internal : std_logic_vector (7 downto 0);
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signal q_a_o_internal : std_logic_vector (7 downto 0);
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signal q_x_o_internal : std_logic_vector (7 downto 0);
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signal q_x_o_internal : std_logic_vector (7 downto 0);
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signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
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signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
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-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
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signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
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signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
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-- ModuleWare signal declarations(v1.9) for instance 'U_10' of 'adff'
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signal mw_U_10reg_cval : std_logic_vector(7 downto 0);
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begin
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begin
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- eb1 1
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val_zero (7 downto 0) <= X"00";
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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q_a_o_internal <= mw_U_0reg_cval;
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q_a_o_internal <= mw_U_0reg_cval;
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u_0seq_proc: process (clk_clk_i, rst_rst_i)
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u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
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begin
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begin
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if (rst_rst_i = '1') then
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if (rst_rst_n_i = '0') then
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mw_U_0reg_cval <= "00000000";
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mw_U_0reg_cval <= "00000000";
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elsif (clk_clk_i'event and clk_clk_i='1') then
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elsif (clk_clk_i'event and clk_clk_i='1') then
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if (load = '1') then
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if (load_o_i = '1') then
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mw_U_0reg_cval <= dout;
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mw_U_0reg_cval <= q_mux_o_i;
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end if;
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end if;
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end if;
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end if;
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end process u_0seq_proc;
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end process u_0seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
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-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
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q_x_o_internal <= mw_U_4reg_cval;
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q_x_o_internal <= mw_U_4reg_cval;
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u_4seq_proc: process (clk_clk_i, rst_rst_i)
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u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
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begin
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begin
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if (rst_rst_i = '1') then
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if (rst_rst_n_i = '0') then
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mw_U_4reg_cval <= "00000000";
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mw_U_4reg_cval <= "00000000";
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elsif (clk_clk_i'event and clk_clk_i='1') then
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elsif (clk_clk_i'event and clk_clk_i='1') then
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if (load1 = '1') then
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if (load1_o_i = '1') then
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mw_U_4reg_cval <= dout;
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mw_U_4reg_cval <= q_mux_o_i;
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end if;
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end if;
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end if;
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end if;
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end process u_4seq_proc;
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end process u_4seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
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-- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
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q_y_o_internal <= mw_U_5reg_cval;
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q_y_o_internal <= mw_U_5reg_cval;
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u_5seq_proc: process (clk_clk_i, rst_rst_i)
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u_5seq_proc: process (clk_clk_i, rst_rst_n_i)
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begin
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begin
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if (rst_rst_i = '1') then
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if (rst_rst_n_i = '0') then
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mw_U_5reg_cval <= "00000000";
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mw_U_5reg_cval <= "00000000";
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elsif (clk_clk_i'event and clk_clk_i='1') then
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elsif (clk_clk_i'event and clk_clk_i='1') then
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if (load2 = '1') then
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if (load2_o_i = '1') then
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mw_U_5reg_cval <= dout;
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mw_U_5reg_cval <= q_mux_o_i;
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end if;
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end if;
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end if;
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end if;
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end process u_5seq_proc;
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end process u_5seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_10' of 'adff'
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q_zw <= mw_U_10reg_cval;
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u_10seq_proc: process (clk_clk_i, rst_rst_i)
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begin
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if (rst_rst_i = '1') then
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mw_U_10reg_cval <= "00000000";
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elsif (clk_clk_i'event and clk_clk_i='1') then
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if (load3 = '1') then
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mw_U_10reg_cval <= dout;
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end if;
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end if;
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end process u_10seq_proc;
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-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
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-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
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load <= load_regs_i and ld(0);
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load_o_i <= load_regs_i and ld(0);
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-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
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-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
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load1 <= load_regs_i and ld(1);
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load1_o_i <= load_regs_i and ld(1);
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-- ModuleWare code(v1.9) for instance 'U_8' of 'and'
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-- ModuleWare code(v1.9) for instance 'U_8' of 'and'
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load2 <= load_regs_i and ld(2);
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load2_o_i <= load_regs_i and ld(2);
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-- ModuleWare code(v1.9) for instance 'U_9' of 'and'
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-- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
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load3 <= load_regs_i and ld(3);
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val_zero <= "00000000";
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-- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
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-- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
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u_1combo_proc: process (sel_reg_i)
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u_1combo_proc: process (sel_reg_i)
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begin
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begin
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ld <= (others => '0');
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ld <= (others => '0');
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case sel_reg_i is
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case sel_reg_i is
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when "00" => ld(0) <= '1';
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when "00" => ld(0) <= '1';
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when "01" => ld(1) <= '1';
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when "01" => ld(1) <= '1';
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when "10" => ld(2) <= '1';
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when "10" => ld(2) <= '1';
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when "11" => ld(3) <= '1';
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when others => ld <= (others => '0');
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when others => ld <= (others => '0');
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end case;
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end case;
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end process u_1combo_proc;
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end process u_1combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
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-- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
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u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
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u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
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q_zw, sel_rb_out_i)
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val_zero, sel_rb_out_i)
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begin
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begin
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case sel_rb_out_i is
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case sel_rb_out_i is
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when "00" => d_regs_out_o <= q_a_o_internal;
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when "00" => d_regs_out_o <= q_a_o_internal;
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when "01" => d_regs_out_o <= q_x_o_internal;
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when "01" => d_regs_out_o <= q_x_o_internal;
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when "10" => d_regs_out_o <= q_y_o_internal;
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when "10" => d_regs_out_o <= q_y_o_internal;
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when "11" => d_regs_out_o <= q_zw;
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when "11" => d_regs_out_o <= val_zero;
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when others => d_regs_out_o <= (others => 'X');
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when others => d_regs_out_o <= (others => 'X');
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end case;
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end case;
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end process u_2combo_proc;
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end process u_2combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
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-- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
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u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
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u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
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d_regs_in_i, sel_rb_in_i(1 DOWNTO 0))
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d_regs_in_i, sel_rb_in_i)
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begin
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begin
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case sel_rb_in_i(1 DOWNTO 0) is
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case sel_rb_in_i is
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when "00" => dout1 <= q_a_o_internal;
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when "00" => q_mux_o_i <= q_a_o_internal;
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when "01" => dout1 <= q_y_o_internal;
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when "01" => q_mux_o_i <= q_y_o_internal;
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when "10" => dout1 <= q_x_o_internal;
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when "10" => q_mux_o_i <= q_x_o_internal;
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when "11" => dout1 <= d_regs_in_i;
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when "11" => q_mux_o_i <= d_regs_in_i;
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when others => dout1 <= (others => 'X');
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when others => q_mux_o_i <= (others => 'X');
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end case;
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end case;
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end process u_3combo_proc;
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end process u_3combo_proc;
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-- ModuleWare code(v1.9) for instance 'U_11' of 'mux'
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u_11combo_proc: process(dout1, q_zw, sel_rb_in_i(2))
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begin
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case sel_rb_in_i(2) is
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when '0' => dout <= dout1;
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when '1' => dout <= q_zw;
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when others => dout <= (others => 'X');
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end case;
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end process u_11combo_proc;
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-- Instance port mappings.
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-- Instance port mappings.
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-- Implicit buffered output assignments
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-- Implicit buffered output assignments
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q_a_o <= q_a_o_internal;
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q_a_o <= q_a_o_internal;
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q_x_o <= q_x_o_internal;
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q_x_o <= q_x_o_internal;
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