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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [regbank_axy.vhd] - Diff between revs 11 and 14

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-- VHDL Entity R6502_TC.RegBank_AXY.symbol
 
-- VHDL Entity R6502_TC.RegBank_AXY.symbol
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (TEST)
 
--          at - 22:53:06 04.01.2009
 
--          at - 18:23:46 07.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_arith.all;
 
USE ieee.std_logic_arith.all;
 
 
 
 
 
entity RegBank_AXY is
 
ENTITY RegBank_AXY IS
 
   port(
 
   PORT(
 
      clk_clk_i    : in     std_logic;
 
      clk_clk_i    : IN     std_logic;
 
      d_regs_in_i  : in     std_logic_vector (7 downto 0);
 
      d_regs_in_i  : IN     std_logic_vector (7 DOWNTO 0);
 
      load_regs_i  : in     std_logic;
 
      load_regs_i  : IN     std_logic;
 
      rst_rst_n_i  : in     std_logic;
 
      rst_rst_n_i  : IN     std_logic;
 
      sel_rb_in_i  : in     std_logic_vector (1 downto 0);
 
      sel_rb_in_i  : IN     std_logic_vector (1 DOWNTO 0);
 
      sel_rb_out_i : in     std_logic_vector (1 downto 0);
 
      sel_rb_out_i : IN     std_logic_vector (1 DOWNTO 0);
 
      sel_reg_i    : in     std_logic_vector (1 downto 0);
 
      sel_reg_i    : IN     std_logic_vector (1 DOWNTO 0);
 
      d_regs_out_o : out    std_logic_vector (7 downto 0);
 
      d_regs_out_o : OUT    std_logic_vector (7 DOWNTO 0);
 
      q_a_o        : out    std_logic_vector (7 downto 0);
 
      q_a_o        : OUT    std_logic_vector (7 DOWNTO 0);
 
      q_x_o        : out    std_logic_vector (7 downto 0);
 
      q_x_o        : OUT    std_logic_vector (7 DOWNTO 0);
 
      q_y_o        : out    std_logic_vector (7 downto 0)
 
      q_y_o        : OUT    std_logic_vector (7 DOWNTO 0)
 
   );
 
   );
 
 
 
 
 
-- Declarations
 
-- Declarations
 
 
 
 
 
end RegBank_AXY ;
 
END RegBank_AXY ;
 
 
 
 
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
--                                                                                                                                             
--
Line 50... Line 50... 
-- Edited:  by eda on 02 Jan 2009  
-- Edited:  by eda on 02 Jan 2009  
--
 
--
 
-- VHDL Architecture R6502_TC.RegBank_AXY.struct
 
-- VHDL Architecture R6502_TC.RegBank_AXY.struct
 
--
 
--
 
-- Created:
 
-- Created:
 
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
 
--          by - eda.UNKNOWN (TEST)
 
--          at - 22:53:07 04.01.2009
 
--          at - 18:23:46 07.01.2009
 
--
 
--
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
 
--
 
--
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_1164.all;
 
USE ieee.std_logic_arith.all;
 
USE ieee.std_logic_arith.all;
 
 
 
 
 
 
 
 
 
architecture struct of RegBank_AXY is
 
ARCHITECTURE struct OF RegBank_AXY IS
 
 
 
 
 
   -- Architecture declarations
 
   -- Architecture declarations
 
 
 
 
 
   -- Internal signal declarations
 
   -- Internal signal declarations
 
   signal ld        : std_logic_vector(2 downto 0);
 
   SIGNAL ld        : std_logic_vector(2 DOWNTO 0);
 
   signal load1_o_i : std_logic;
 
   SIGNAL load1_o_i : std_logic;
 
   signal load2_o_i : std_logic;
 
   SIGNAL load2_o_i : std_logic;
 
   signal load_o_i  : std_logic;
 
   SIGNAL load_o_i  : std_logic;
 
   signal q_mux_o_i : std_logic_vector(7 downto 0);
 
   SIGNAL q_mux_o_i : std_logic_vector(7 DOWNTO 0);
 
   signal val_zero  : std_logic_vector(7 downto 0);
 
   SIGNAL val_zero  : std_logic_vector(7 DOWNTO 0);
 
 
 
 
 
   -- Implicit buffer signal declarations
 
   -- Implicit buffer signal declarations
 
   signal q_a_o_internal : std_logic_vector (7 downto 0);
 
   SIGNAL q_a_o_internal : std_logic_vector (7 DOWNTO 0);
 
   signal q_x_o_internal : std_logic_vector (7 downto 0);
 
   SIGNAL q_x_o_internal : std_logic_vector (7 DOWNTO 0);
 
   signal q_y_o_internal : std_logic_vector (7 downto 0);
 
   SIGNAL q_y_o_internal : std_logic_vector (7 DOWNTO 0);
 
 
 
 
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
 
   signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
   SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
 
   signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
 
   SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
 
 
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
 
   -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
 
   signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
 
   SIGNAL mw_U_5reg_cval : std_logic_vector(7 DOWNTO 0);
 
 
 
 
 
 
 
 
 
begin
 
BEGIN
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
 
   q_a_o_internal <= mw_U_0reg_cval;
 
   q_a_o_internal <= mw_U_0reg_cval;
 
   u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
 
   u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
 
   begin
 
   BEGIN
 
      if (rst_rst_n_i = '0') then
 
      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
 
         mw_U_0reg_cval <= "00000000";
 
         mw_U_0reg_cval <= "00000000";
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
 
         if (load_o_i = '1') then
 
         IF (load_o_i = '1' OR load_o_i = 'H') THEN
 
            mw_U_0reg_cval <= q_mux_o_i;
 
            mw_U_0reg_cval <= q_mux_o_i;
 
         end if;
 
         END IF;
 
      end if;
 
      END IF;
 
   end process u_0seq_proc;
 
   END PROCESS u_0seq_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
 
   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
 
   q_x_o_internal <= mw_U_4reg_cval;
 
   q_x_o_internal <= mw_U_4reg_cval;
 
   u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
 
   u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
 
   begin
 
   BEGIN
 
      if (rst_rst_n_i = '0') then
 
      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
 
         mw_U_4reg_cval <= "00000000";
 
         mw_U_4reg_cval <= "00000000";
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
 
         if (load1_o_i = '1') then
 
         IF (load1_o_i = '1' OR load1_o_i = 'H') THEN
 
            mw_U_4reg_cval <= q_mux_o_i;
 
            mw_U_4reg_cval <= q_mux_o_i;
 
         end if;
 
         END IF;
 
      end if;
 
      END IF;
 
   end process u_4seq_proc;
 
   END PROCESS u_4seq_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
 
   -- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
 
   q_y_o_internal <= mw_U_5reg_cval;
 
   q_y_o_internal <= mw_U_5reg_cval;
 
   u_5seq_proc: process (clk_clk_i, rst_rst_n_i)
 
   u_5seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
 
   begin
 
   BEGIN
 
      if (rst_rst_n_i = '0') then
 
      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN
 
         mw_U_5reg_cval <= "00000000";
 
         mw_U_5reg_cval <= "00000000";
 
      elsif (clk_clk_i'event and clk_clk_i='1') then
 
      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
 
         if (load2_o_i = '1') then
 
         IF (load2_o_i = '1' OR load2_o_i = 'H') THEN
 
            mw_U_5reg_cval <= q_mux_o_i;
 
            mw_U_5reg_cval <= q_mux_o_i;
 
         end if;
 
         END IF;
 
      end if;
 
      END IF;
 
   end process u_5seq_proc;
 
   END PROCESS u_5seq_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
 
   load_o_i <= load_regs_i and ld(0);
 
   load_o_i <= load_regs_i AND ld(0);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'
 
   load1_o_i <= load_regs_i and ld(1);
 
   load1_o_i <= load_regs_i AND ld(1);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'and'
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'and'
 
   load2_o_i <= load_regs_i and ld(2);
 
   load2_o_i <= load_regs_i AND ld(2);
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
 
   val_zero <= "00000000";
 
   val_zero <= "00000000";
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
 
   -- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
 
   u_1combo_proc: process (sel_reg_i)
 
   u_1combo_proc: PROCESS (sel_reg_i)
 
   begin
 
   BEGIN
 
      ld <= (others => '0');
 
      ld <= (OTHERS => '0');
 
      case sel_reg_i is
 
      CASE sel_reg_i IS
 
         when "00" => ld(0) <= '1';
 
         WHEN "00" => ld(0) <= '1';
 
         when "01" => ld(1) <= '1';
 
         WHEN "01" => ld(1) <= '1';
 
         when "10" => ld(2) <= '1';
 
         WHEN "10" => ld(2) <= '1';
 
         when others => ld <= (others => '0');
 
         WHEN OTHERS => ld <= (OTHERS => '0');
 
      end case;
 
      END CASE;
 
   end process u_1combo_proc;
 
   END PROCESS u_1combo_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
 
   -- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
 
   u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
 
   u_2combo_proc: PROCESS(q_a_o_internal, q_x_o_internal, q_y_o_internal,
 
                          val_zero, sel_rb_out_i)
 
                          val_zero, sel_rb_out_i)
 
   begin
 
   BEGIN
 
      case sel_rb_out_i is
 
      CASE sel_rb_out_i IS
 
      when "00" => d_regs_out_o <= q_a_o_internal;
 
      WHEN "00"|"L0"|"0L"|"LL" => d_regs_out_o <= q_a_o_internal;
 
      when "01" => d_regs_out_o <= q_x_o_internal;
 
      WHEN "01"|"L1"|"0H"|"LH" => d_regs_out_o <= q_x_o_internal;
 
      when "10" => d_regs_out_o <= q_y_o_internal;
 
      WHEN "10"|"H0"|"1L"|"HL" => d_regs_out_o <= q_y_o_internal;
 
      when "11" => d_regs_out_o <= val_zero;
 
      WHEN "11"|"H1"|"1H"|"HH" => d_regs_out_o <= val_zero;
 
      when others => d_regs_out_o <= (others => 'X');
 
      WHEN OTHERS => d_regs_out_o <= (OTHERS => 'X');
 
      end case;
 
      END CASE;
 
   end process u_2combo_proc;
 
   END PROCESS u_2combo_proc;
 
 
 
 
 
   -- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
 
   -- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
 
   u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
 
   u_3combo_proc: PROCESS(q_a_o_internal, q_y_o_internal, q_x_o_internal,
 
                          d_regs_in_i, sel_rb_in_i)
 
                          d_regs_in_i, sel_rb_in_i)
 
   begin
 
   BEGIN
 
      case sel_rb_in_i is
 
      CASE sel_rb_in_i IS
 
      when "00" => q_mux_o_i <= q_a_o_internal;
 
      WHEN "00"|"L0"|"0L"|"LL" => q_mux_o_i <= q_a_o_internal;
 
      when "01" => q_mux_o_i <= q_y_o_internal;
 
      WHEN "01"|"L1"|"0H"|"LH" => q_mux_o_i <= q_y_o_internal;
 
      when "10" => q_mux_o_i <= q_x_o_internal;
 
      WHEN "10"|"H0"|"1L"|"HL" => q_mux_o_i <= q_x_o_internal;
 
      when "11" => q_mux_o_i <= d_regs_in_i;
 
      WHEN "11"|"H1"|"1H"|"HH" => q_mux_o_i <= d_regs_in_i;
 
      when others => q_mux_o_i <= (others => 'X');
 
      WHEN OTHERS => q_mux_o_i <= (OTHERS => 'X');
 
      end case;
 
      END CASE;
 
   end process u_3combo_proc;
 
   END PROCESS u_3combo_proc;
 
 
 
 
 
   -- Instance port mappings.
 
   -- Instance port mappings.
 
 
 
 
 
   -- Implicit buffered output assignments
 
   -- Implicit buffered output assignments
 
   q_a_o <= q_a_o_internal;
 
   q_a_o <= q_a_o_internal;
 
   q_x_o <= q_x_o_internal;
 
   q_x_o <= q_x_o_internal;
 
   q_y_o <= q_y_o_internal;
 
   q_y_o <= q_y_o_internal;
 
 
 
 
 
end struct;
 
END struct;
 
 
 
 
 
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