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[/] [cpu65c02_true_cycle/] [trunk/] [TO_DO_list.txt] - Diff between revs 18 and 20
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Rev 18 |
Rev 20 |
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(September 09th 2018)
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- (WORKING) Performance improvements
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- (WORKING) Creating test strategy for RDY signal
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- (DONE) Working on reported Bugs/Requests: JMP, Branches, Interrupts, ADC/SBC
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- (DONE) Verifying all interrupts
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- (90%) Finish working for Specification of cpu65C02_tc
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(July 31th 2013)
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(July 31th 2013)
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- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"
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- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"
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- (DONE) Offer a high level testbench in assembler for testing all Op Codes
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- (DONE) Offer a high level testbench in assembler for testing all Op Codes
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Including Klaus Dormann's "65c02_*_test" suite
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Including Klaus Dormann's "65c02_*_test" suite
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- (DONE) Because of translation errors the Verilog sources are no longer
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- (DONE) Because of translation errors the Verilog sources are no longer
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