OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [branches/] [samiam95124/] [project/] [cpu8080.ucf] - Diff between revs 18 and 24

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 18 Rev 24
Line 1... Line 1...
#PACE: Start of Constraints generated by PACE
#PACE: Start of Constraints generated by PACE
 
 
#PACE: Start of PACE I/O Pin Assignments
#PACE: Start of PACE I/O Pin Assignments
NET "addr<0>"  LOC = "g1"  ;
NET "addr<0>"  LOC = "g1"  ;
 
NET "addr<10>"  LOC = "l3"  ;
 
NET "addr<11>"  LOC = "m1"  ;
 
NET "addr<12>"  LOC = "m2"  ;
 
NET "addr<13>"  LOC = "l4"  ;
 
NET "addr<14>"  LOC = "n1"  ;
NET "addr<1>"  LOC = "h4"  ;
NET "addr<1>"  LOC = "h4"  ;
NET "addr<2>"  LOC = "h3"  ;
NET "addr<2>"  LOC = "h3"  ;
NET "addr<3>"  LOC = "h1"  ;
NET "addr<3>"  LOC = "h1"  ;
NET "addr<4>"  LOC = "j1"  ;
NET "addr<4>"  LOC = "j1"  ;
NET "addr<5>"  LOC = "j2"  ;
NET "addr<5>"  LOC = "j2"  ;
NET "addr<6>"  LOC = "j3"  ;
NET "addr<6>"  LOC = "j3"  ;
NET "addr<7>"  LOC = "k1"  ;
NET "addr<7>"  LOC = "k1"  ;
 
NET "addr<8>"  LOC = "l2"  ;
 
NET "addr<9>"  LOC = "k5"  ;
NET "b<0>"  LOC = "c9"  ;
NET "b<0>"  LOC = "c9"  ;
NET "b<1>"  LOC = "e7"  ;
NET "b<1>"  LOC = "e7"  ;
NET "b<2>"  LOC = "d5"  ;
NET "b<2>"  LOC = "d5"  ;
NET "clock"  LOC = "p8"  ;
NET "clock"  LOC = "p8"  ;
NET "data<0>"  LOC = "e2"  ;
NET "data<0>"  LOC = "e2"  ;
Line 19... Line 26...
NET "data<3>"  LOC = "g5"  ;
NET "data<3>"  LOC = "g5"  ;
NET "data<4>"  LOC = "f2"  ;
NET "data<4>"  LOC = "f2"  ;
NET "data<5>"  LOC = "g4"  ;
NET "data<5>"  LOC = "g4"  ;
NET "data<6>"  LOC = "g3"  ;
NET "data<6>"  LOC = "g3"  ;
NET "data<7>"  LOC = "g2"  ;
NET "data<7>"  LOC = "g2"  ;
NET "diag<0>"  LOC = "l2"  ;
 
NET "diag<1>"  LOC = "k5"  ;
 
NET "diag<2>"  LOC = "l3"  ;
 
NET "diag<3>"  LOC = "m1"  ;
 
NET "diag<4>"  LOC = "m2"  ;
 
NET "diag<5>"  LOC = "l4"  ;
 
NET "diag<6>"  LOC = "n1"  ;
 
NET "diag<7>"  LOC = "m3"  ;
NET "diag<7>"  LOC = "m3"  ;
NET "g<0>"  LOC = "A8"  ;
NET "g<0>"  LOC = "A8"  ;
NET "g<1>"  LOC = "A5"  ;
NET "g<1>"  LOC = "A5"  ;
NET "g<2>"  LOC = "C3"  ;
NET "g<2>"  LOC = "C3"  ;
NET "hsync_n"  LOC = "B7"  ;
NET "hsync_n"  LOC = "B7"  ;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.