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URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [branches/] [samiam95124/] [project/] [cpu8080_tbw.tbw] - Diff between revs 18 and 28

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Rev 18	Rev 28
Line 5...	Line 5...
`VERILOG`	`VERILOG`
`cpu8080_tbw.xwv`	`cpu8080_tbw.xwv`
`Clocked`	`Clocked`
`-`	`-`
`-`	`-`
`100000000000`	`200000000000`
`ns`	`ns`
`GSR:true`	`GSR:true`
`PRLD:false`	`PRLD:false`
`100000000`	`100000000`
`CLOCK_LIST_BEGIN`	`CLOCK_LIST_BEGIN`
Line 26...	Line 26...
`clock`	`clock`
`b`	`b`
`clock`	`clock`
`data`	`data`
`clock`	`clock`
	`diag`
	`clock`
`g`	`g`
`clock`	`clock`
`hsync_n`	`hsync_n`
`clock`	`clock`
`inta`	`inta`
Line 60...	Line 62...
`clock`	`clock`
`SIGNAL_LIST_END`	`SIGNAL_LIST_END`
`SIGNALS_NOT_ON_DISPLAY`	`SIGNALS_NOT_ON_DISPLAY`
`addr_DIFF`	`addr_DIFF`
`b_DIFF`	`b_DIFF`
	`diag_DIFF`
`g_DIFF`	`g_DIFF`
`hsync_n_DIFF`	`hsync_n_DIFF`
`inta_DIFF`	`inta_DIFF`
`intr_DIFF`	`intr_DIFF`
`r_DIFF`	`r_DIFF`
`readio_DIFF`	`readio_DIFF`
`readmem_DIFF`	`readmem_DIFF`
`vsync_n_DIFF`	`vsync_n_DIFF`
	`waitr_DIFF`
`writeio_DIFF`	`writeio_DIFF`
`writemem_DIFF`	`writemem_DIFF`
`SIGNALS_NOT_ON_DISPLAY_END`	`SIGNALS_NOT_ON_DISPLAY_END`
`MARKER_LIST_BEGIN`	`MARKER_LIST_BEGIN`
`MARKER_LIST_END`	`MARKER_LIST_END`
Line 94...	Line 98...
`r`	`r`
`hsync_n`	`hsync_n`
`vsync_n`	`vsync_n`
`ps2_clk`	`ps2_clk`
`ps2_data`	`ps2_data`
	`diag`
`SIGNAL_ORDER_END`	`SIGNAL_ORDER_END`
`-X-X-X-`	`-X-X-X-`

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