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[/] [cpu8080/] [tags/] [update/] [project/] [cpu_tbw.tbw] - Diff between revs 2 and 11

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Rev 2	Rev 11
Line 5...	Line 5...
`VERILOG`	`VERILOG`
`cpu_tbw.xwv`	`cpu_tbw.xwv`
`Clocked`	`Clocked`
`-`	`-`
`-`	`-`
`10000000000`	`100000000000`
`ns`	`ns`
`GSR:false`	`GSR:false`
`PRLD:false`	`PRLD:false`
`100000000`	`100000000`
`CLOCK_LIST_BEGIN`	`CLOCK_LIST_BEGIN`
Line 22...	Line 22...
`RISING`	`RISING`
`CLOCK_LIST_END`	`CLOCK_LIST_END`
`SIGNAL_LIST_BEGIN`	`SIGNAL_LIST_BEGIN`
`addr`	`addr`
`clock`	`clock`
	`b`
	`clock`
`data`	`data`
`clock`	`clock`
	`g`
	`clock`
	`hsync_n`
	`clock`
`inta`	`inta`
`clock`	`clock`
`intr`	`intr`
`clock`	`clock`
`junk`	`junk`
`clock`	`clock`
	`r`
	`clock`
`readio`	`readio`
`clock`	`clock`
`readmem`	`readmem`
`clock`	`clock`
`reset`	`reset`
`clock`	`clock`
	`vsync_n`
	`clock`
`waitr`	`waitr`
`clock`	`clock`
`writeio`	`writeio`
`clock`	`clock`
`writemem`	`writemem`
`clock`	`clock`
`SIGNAL_LIST_END`	`SIGNAL_LIST_END`
`SIGNALS_NOT_ON_DISPLAY`	`SIGNALS_NOT_ON_DISPLAY`
`addr_DIFF`	`addr_DIFF`
	`b_DIFF`
	`g_DIFF`
	`hsync_n_DIFF`
`inta_DIFF`	`inta_DIFF`
	`intr_DIFF`
	`r_DIFF`
`readio_DIFF`	`readio_DIFF`
`readmem_DIFF`	`readmem_DIFF`
	`vsync_n_DIFF`
`writeio_DIFF`	`writeio_DIFF`
`writemem_DIFF`	`writemem_DIFF`
`SIGNALS_NOT_ON_DISPLAY_END`	`SIGNALS_NOT_ON_DISPLAY_END`
`MARKER_LIST_BEGIN`	`MARKER_LIST_BEGIN`
`MARKER_LIST_END`	`MARKER_LIST_END`
Line 67...	Line 83...
`readmem`	`readmem`
`writeio`	`writeio`
`writemem`	`writemem`
`addr`	`addr`
`data`	`data`
	`b`
	`g`
	`r`
	`hsync_n`
	`vsync_n`
`SIGNAL_ORDER_END`	`SIGNAL_ORDER_END`
`-X-X-X-`	`-X-X-X-`

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