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Release 8.2.02i par I.33
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Release 8.2.02i par I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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SCOTT-H-PC:: Thu Nov 16 20:11:54 2006
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SCOTT-H-PC:: Sat Nov 18 17:12:12 2006
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par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf
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par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf
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Constraints file: testbench.pcf.
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Constraints file: testbench.pcf.
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Line 28... |
Number of External IOBs 54 out of 173 31%
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Number of External IOBs 54 out of 173 31%
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Number of LOCed IOBs 46 out of 54 85%
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Number of LOCed IOBs 46 out of 54 85%
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Number of MULT18X18s 2 out of 24 8%
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Number of MULT18X18s 2 out of 24 8%
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Number of RAMB16s 4 out of 24 16%
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Number of RAMB16s 4 out of 24 16%
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Number of Slices 3445 out of 7680 44%
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Number of Slices 3447 out of 7680 44%
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Number of SLICEMs 958 out of 3840 24%
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Number of SLICEMs 958 out of 3840 24%
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Overall effort level (-ol): Standard
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Overall effort level (-ol): Standard
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| Line 42... |
Line 42... |
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Starting Placer
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Starting Placer
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Phase 1.1
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Phase 1.1
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Phase 1.1 (Checksum:99838d) REAL time: 8 secs
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Phase 1.1 (Checksum:998412) REAL time: 11 secs
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Phase 2.7
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Phase 2.7
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WARNING:Place:837 - Partially locked IO Bus is found.
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WARNING:Place:837 - Partially locked IO Bus is found.
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Following components of the bus are not locked:
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Following components of the bus are not locked:
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Comp: addr<15>
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Comp: addr<15>
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Line 61... |
Comp: diag<1>
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Comp: diag<1>
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Comp: diag<0>
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Comp: diag<0>
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INFO:Place:834 - Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like
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INFO:Place:834 - Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like
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to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more).
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to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more).
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Phase 2.7 (Checksum:1312cfe) REAL time: 8 secs
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Phase 2.7 (Checksum:1312cfe) REAL time: 11 secs
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Phase 3.31
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Phase 3.31
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Phase 3.31 (Checksum:1c9c37d) REAL time: 8 secs
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Phase 3.31 (Checksum:1c9c37d) REAL time: 11 secs
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Phase 4.2
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Phase 4.2
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.....
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.....
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...................
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...................
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Phase 4.2 (Checksum:98bdc7) REAL time: 16 secs
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Phase 4.2 (Checksum:98bdc7) REAL time: 21 secs
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Phase 5.3
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Phase 5.3
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Phase 5.3 (Checksum:2faf07b) REAL time: 17 secs
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Phase 5.3 (Checksum:2faf07b) REAL time: 21 secs
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Phase 6.5
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Phase 6.5
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Phase 6.5 (Checksum:39386fa) REAL time: 17 secs
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Phase 6.5 (Checksum:39386fa) REAL time: 22 secs
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Phase 7.8
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Phase 7.8
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......................................................................................................................................................................................
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.......................................................................................................................................................................................................
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.........
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.......................................................................................................................................................
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..........
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..........
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............
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...................................................................................................................................................
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.......................
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.........
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Phase 7.8 (Checksum:124efe7) REAL time: 1 mins 42 secs
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.........
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..............
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Phase 7.8 (Checksum:11c59cb) REAL time: 2 mins
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Phase 8.5
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Phase 8.5
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 mins 42 secs
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins
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Phase 9.18
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Phase 9.18
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Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 44 secs
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Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 47 secs
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Phase 10.5
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Phase 10.5
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Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 44 secs
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Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 47 secs
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Writing design to file testbench.ncd
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Writing design to file testbench.ncd
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Total REAL time to Placer completion: 2 mins 48 secs
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Total REAL time to Placer completion: 2 mins 51 secs
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Total CPU time to Placer completion: 2 mins 42 secs
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Total CPU time to Placer completion: 2 mins 37 secs
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Starting Router
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Starting Router
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Phase 1: 27650 unrouted; REAL time: 2 mins 49 secs
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Phase 1: 27602 unrouted; REAL time: 2 mins 52 secs
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Phase 2: 26038 unrouted; REAL time: 2 mins 57 secs
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Phase 3: 8278 unrouted; REAL time: 3 mins 4 secs
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Phase 4: 8278 unrouted; (42106) REAL time: 3 mins 4 secs
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Phase 2: 25995 unrouted; REAL time: 3 mins 1 secs
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Phase 5: 8305 unrouted; (0) REAL time: 3 mins 7 secs
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Phase 3: 8138 unrouted; REAL time: 3 mins 9 secs
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Phase 6: 0 unrouted; (8000) REAL time: 3 mins 44 secs
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Phase 4: 8138 unrouted; (22222) REAL time: 3 mins 9 secs
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Phase 7: 0 unrouted; (8000) REAL time: 3 mins 47 secs
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Phase 5: 8108 unrouted; (0) REAL time: 3 mins 12 secs
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Phase 8: 0 unrouted; (5730) REAL time: 4 mins
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Phase 6: 0 unrouted; (0) REAL time: 3 mins 44 secs
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Phase 9: 0 unrouted; (5730) REAL time: 4 mins 9 secs
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Phase 7: 0 unrouted; (0) REAL time: 3 mins 48 secs
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WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because
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WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because
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462 NON-CLK pins failed to route using a CLK template.
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464 NON-CLK pins failed to route using a CLK template.
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Total REAL time to Router completion: 4 mins 9 secs
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Total REAL time to Router completion: 3 mins 48 secs
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Total CPU time to Router completion: 3 mins 57 secs
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Total CPU time to Router completion: 3 mins 31 secs
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Partition Implementation Status
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Partition Implementation Status
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-------------------------------
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-------------------------------
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No Partitions were found in this design.
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No Partitions were found in this design.
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Line 141... |
**************************
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| clock_BUFGP | BUFGMUX3| No | 1382 | 0.433 | 1.139 |
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| clock_BUFGP | BUFGMUX3| No | 1378 | 0.461 | 1.164 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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| reset_n_BUFGP | BUFGMUX5| No | 478 | 0.155 | 1.085 |
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| reset_n_BUFGP | BUFGMUX5| No | 480 | 0.251 | 0.972 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectc/_and | | | | | |
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|select1/selectc/_and | | | | | |
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| 0000 | Local| | 7 | 0.156 | 3.257 |
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| 0000 | Local| | 7 | 0.187 | 3.279 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selecta/_and | | | | | |
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|select1/selecta/_and | | | | | |
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| 0000 | Local| | 7 | 0.085 | 2.938 |
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| 0000 | Local| | 7 | 0.048 | 2.205 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectd/_and | | | | | |
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|select1/selectd/_and | | | | | |
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| 0000 | Local| | 7 | 0.131 | 2.884 |
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| 0000 | Local| | 7 | 0.193 | 2.324 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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|select1/selectb/_and | | | | | |
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|select1/selectb/_and | | | | | |
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| 0000 | Local| | 7 | 0.079 | 2.261 |
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| 0000 | Local| | 7 | 0.177 | 2.932 |
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+---------------------+--------------+------+------+------------+-------------+
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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is reported in TRCE timing report. Clock Skew is the difference between
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Line 169... |
The Delay Summary Report
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The Delay Summary Report
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The AVERAGE CONNECTION DELAY for this design is: 2.351
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The AVERAGE CONNECTION DELAY for this design is: 2.287
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The MAXIMUM PIN DELAY IS: 9.448
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The MAXIMUM PIN DELAY IS: 9.510
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.536
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.894
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Listing Pin Delays by value: (nsec)
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Listing Pin Delays by value: (nsec)
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d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 10.00 d >= 10.00
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d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 10.00 d >= 10.00
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--------- --------- --------- --------- --------- ---------
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--------- --------- --------- --------- --------- ---------
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14494 8705 3462 1202 93 0
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14560 8731 3770 745 98 0
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Timing Score: 0
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Timing Score: 0
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Asterisk (*) preceding a constraint indicates it was not met.
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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Constraint | Requested | Actual | Logic | Absolute |Number of
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Constraint | Requested | Actual | Logic | Absolute |Number of
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| | | Levels | Slack |errors
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| | | Levels | Slack |errors
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clo | N/A | 20.711ns | 4 | N/A | N/A
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Autotimespec constraint for clock net clo | N/A | 20.098ns | 8 | N/A | N/A
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ck_BUFGP | | | | |
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ck_BUFGP | | | | |
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------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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All constraints were met.
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Line 202... |
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Generating Pad Report.
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Generating Pad Report.
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All signals are completely routed.
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All signals are completely routed.
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Total REAL time to PAR completion: 4 mins 20 secs
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Total REAL time to PAR completion: 3 mins 56 secs
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Total CPU time to PAR completion: 4 mins 2 secs
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Total CPU time to PAR completion: 3 mins 38 secs
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Peak Memory Usage: 283 MB
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Peak Memory Usage: 269 MB
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Placement: Completed - No errors found.
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of error messages: 0
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