| Line 29... |
Line 29... |
inta, // Interrupt request
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inta, // Interrupt request
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waitr, // Wait request
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waitr, // Wait request
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r, g, b, // vga colors
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r, g, b, // vga colors
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hsync_n, // vga horizontal sync negative
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hsync_n, // vga horizontal sync negative
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vsync_n, // vga vertical sync negative
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vsync_n, // vga vertical sync negative
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ps2_clk, // keyboard clock
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ps2_data, // keyboard data
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reset_n, // Reset
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reset_n, // Reset
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clock); // System clock
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clock, // System clock
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diag); // diagnostic port
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output [15:0] addr;
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output [15:0] addr;
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inout [7:0] data;
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inout [7:0] data;
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output readmem;
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output readmem;
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output writemem;
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output writemem;
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output readio;
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output readio;
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output writeio;
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output writeio;
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output intr;
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output intr;
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output inta;
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output inta;
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input waitr;
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output waitr;
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output [2:0] r, g, b; // R,G,B color output buses
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output [2:0] r, g, b; // R,G,B color output buses
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output hsync_n; // horizontal sync pulse
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output hsync_n; // horizontal sync pulse
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output vsync_n; // vertical sync pulse
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output vsync_n; // vertical sync pulse
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input ps2_clk; // clock from keyboard
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input ps2_data; // data from keyboard
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input reset_n;
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input reset_n;
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input clock;
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input clock;
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output [7:0] diag; // diagnostic 8 bit port
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reg [7:0] clkdiv;
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wire clocki;
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wire reset;
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initial clkdiv = 0;
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// divide down the clock so we can debug
|
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always @(posedge clock) clkdiv <= clkdiv+1; // count
|
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assign clocki = clkdiv[3]; // pick off top bit as internal clock
|
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// assign clocki = clock;
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|
|
//
|
//
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// Instantiations
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// Instantiations
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//
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//
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|
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// selector block, we only use select 1, 2 and 3
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// selector block, we only use select 1, 2 and 3
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select select1(addr, data, readio, writeio, romsel, ramsel, intsel,
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select select1(addr, data, readio, writeio, romsel, ramsel, intsel,
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trmsel, bootstrap, clocki, reset);
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trmsel, bootstrap, clock, reset);
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|
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// 8080 CPU
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// 8080 CPU
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cpu8080 cpu(addr, data, readmem, writemem, readio, writeio, intr, inta, waitr,
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cpu8080 cpu(addr, data, readmem, writemem, readio, writeio, intr, inta, waitr,
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reset, clocki);
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reset, clock);
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// assign readmem = 0;
|
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// assign writemem = 0;
|
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// assign readio = 0;
|
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// assign writeio = 0;
|
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// assign inta = 0;
|
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// assign addr = 0;
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|
|
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// Program rom
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// Program rom
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rom rom(addr[9:0], data, romsel&readmem); // unclocked rom
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rom rom(addr[9:0], data, romsel&readmem); // unclocked rom
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|
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// neg clocked ram
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// neg clocked ram
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ram ram(addr[9:0], data, ramsel, readmem, writemem, bootstrap, clocki);
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ram ram(addr[9:0], data, ramsel, readmem, writemem, bootstrap, clock);
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|
|
// neg clocked interrupt controller
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// neg clocked interrupt controller
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intcontrol intc(addr[2:0], data, writeio, readio, intsel, intr, inta, int0, int1,
|
intcontrol intc(addr[2:0], data, writeio, readio, intsel, intr, inta, int0, int1,
|
int2, int3, int4, int5, int6, int7, reset, clocki);
|
int2, int3, int4, int5, int6, int7, reset, clock);
|
|
|
// ADM3A dumb terminal
|
// ADM3A dumb terminal
|
terminal adm3a(addr[0], data, writeio, readio, trmsel, r, g, b, hsync_n, vsync_n,
|
terminal adm3a(addr[0], data, writeio, readio, trmsel, r, g, b, hsync_n, vsync_n,
|
reset, clock);
|
ps2_clk, ps2_data, reset, clock, diag);
|
|
|
// generate reset
|
// generate reset
|
assign reset = !reset_n;
|
assign reset = !reset_n;
|
|
|
// pull up unused interrupt lines
|
// pull up or down unused lines
|
assign int0 = 1;
|
assign int0 = 0;
|
assign int1 = 1;
|
assign int1 = 0;
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assign int2 = 1;
|
assign int2 = 0;
|
assign int3 = 1;
|
assign int3 = 0;
|
assign int4 = 1;
|
assign int4 = 0;
|
assign int5 = 1;
|
assign int5 = 0;
|
assign int6 = 1;
|
assign int6 = 0;
|
assign int7 = 1;
|
assign int7 = 0;
|
|
assign waitr = 0;
|
|
|
endmodule
|
endmodule
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
| Line 564... |
Line 554... |
|
|
reg [7:0] datao;
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reg [7:0] datao;
|
|
|
always @(addr) case (addr)
|
always @(addr) case (addr)
|
|
|
`include "test.lst" // get contents of memory
|
`include "test.rom" // get contents of memory
|
|
|
default datao = 8'h76; // hlt
|
default datao = 8'h76; // hlt
|
|
|
endcase
|
endcase
|
|
|
