The function generator adm3a/display/chradr<4>81 failed to merge with F5 multiplexer adm3a/display/chradr<5>_f5_62. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
The function generator adm3a/display/chradr<5>35 failed to merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux0003. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux00071_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Dangling pin <DOA5> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
Dangling pin <DOA6> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
Dangling pin <DOA7> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
