URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [_xmsgs/] [netgen.xmsgs] - Diff between revs 2 and 11

Rev 2	Rev 11
Line 3...	Line 3...
`by the Xilinx ISE software. Any direct editing or`	`by the Xilinx ISE software. Any direct editing or`
`changes made to this file may result in unpredictable`	`changes made to this file may result in unpredictable`
`behavior or data corruption. It is strongly advised that`	`behavior or data corruption. It is strongly advised that`
`users do not edit the contents of this file. -->`	`users do not edit the contents of this file. -->`

`The generated Verilog netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM simulation library for correct compilation and simulation.`	`The generated Verilog netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM simulation library for correct compilation and simulation.`