No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med".
No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med".
CLK Net:reset_n_BUFGP may have excessive skew because
Partially locked IO Bus is found.
Following components of the bus are not locked:
Comp: addr<15>
Comp: addr<14>
Comp: addr<13>
Comp: addr<12>
Comp: addr<11>
Comp: addr<10>
Comp: addr<9>
Comp: addr<8>
Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more).
CLK Net:clkdiv<3> may have excessive skew because
CLK Net:reset_n_BUFGP may have excessive skew because
N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.
N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.
