| Line 3... |
Line 3... |
by the Xilinx ISE software. Any direct editing or
|
by the Xilinx ISE software. Any direct editing or
|
changes made to this file may result in unpredictable
|
changes made to this file may result in unpredictable
|
behavior or data corruption. It is strongly advised that
|
behavior or data corruption. It is strongly advised that
|
users do not edit the contents of this file. -->
|
users do not edit the contents of this file. -->
|
|
|
Contents of register <cmread> in unit <terminal> never changes during circuit operation. The register is replaced by logic.
|
|
|
|
|
|
Input <addr<9:8>> is never used.
|
Input <addr<9:8>> is never used.
|
|
|
|
|
Input <addr<1>> is never used.
|
Input <addr<1>> is never used.
|
|
|
| Line 24... |
Line 21... |
|
|
|
|
Signal <resi> is assigned but never used.
|
Signal <resi> is assigned but never used.
|
|
|
|
|
|
Signal <keyrel_r> is assigned but never used.
|
|
|
|
|
|
State 0XXXXX is never reached in FSM <state>.
|
|
|
|
|
Signal <line_cnt> is assigned but never used.
|
Signal <line_cnt> is assigned but never used.
|
|
|
|
|
Signal <pixel_cnt<15:4>> is assigned but never used.
|
Signal <pixel_cnt<15:4>> is assigned but never used.
|
|
|
| Line 36... |
Line 39... |
|
|
|
|
HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
|
HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
|
|
|
|
|
HDL ADVISOR - Mux Selector <fchsta> of Case statement line 320 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
|
HDL ADVISOR - Mux Selector <fchsta> of Case statement line 654 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
|
- add an 'INIT' attribute on signal <fchsta> (optimization is then done without any risk)
|
- add an 'INIT' attribute on signal <fchsta> (optimization is then done without any risk)
|
- use the attribute 'signal_encoding user' to avoid onehot optimization
|
- use the attribute 'signal_encoding user' to avoid onehot optimization
|
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
|
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
|
|
|
|
|
"vgachr.v" line 361: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
|
"vgachr.v" line 706: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
|
|
|
|
|
HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
|
|
|
|
|
FFs/Latches <chrdatw<7:7>> (without init value) have a constant value of 0 in block <terminal>.
|
|
|
|
|
|
Address input of ROM <rom/Mrom__mux0000> is tied to register <cpu/addr>.
|
|
|
|
|
|
The register is removed and the ROM is implemented as read-only block RAM.
|
Signal <parity> is assigned but never used.
|
|
|
|
|
The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8>
|
Signal <error> is assigned but never used.
|
|
|
|
|
FF/Latch <datai_0> (without init value) has a constant value of 0 in block <select>.
|
HDL ADVISOR - Mux Selector <state> of Case statement line 296 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
|
|
- add an 'INIT' attribute on signal <state> (optimization is then done without any risk)
|
|
- use the attribute 'signal_encoding user' to avoid onehot optimization
|
|
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datai_1> (without init value) has a constant value of 0 in block <select>.
|
HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datai_2> (without init value) has a constant value of 0 in block <select>.
|
FFs/Latches <curchr<7:7>> (without init value) have a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datai_3> (without init value) has a constant value of 0 in block <select>.
|
FFs/Latches <chrdatw<7:7>> (without init value) have a constant value of 0 in block <terminal>.
|
|
|
|
|
FF/Latch <datao_0> (without init value) has a constant value of 0 in block <terminal>.
|
Address input of ROM <rom/Mrom__mux0000> is tied to register <cpu/addr>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datao_1> (without init value) has a constant value of 0 in block <terminal>.
|
The register is removed and the ROM is implemented as read-only block RAM.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datao_2> (without init value) has a constant value of 0 in block <terminal>.
|
FF/Latch <datai_0> (without init value) has a constant value of 0 in block <select>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datao_3> (without init value) has a constant value of 0 in block <terminal>.
|
Due to other FF/Latch trimming, FF/Latch <datai_1> (without init value) has a constant value of 0 in block <select>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datao_4> (without init value) has a constant value of 0 in block <terminal>.
|
Due to other FF/Latch trimming, FF/Latch <datai_2> (without init value) has a constant value of 0 in block <select>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datao_5> (without init value) has a constant value of 0 in block <terminal>.
|
Due to other FF/Latch trimming, FF/Latch <datai_3> (without init value) has a constant value of 0 in block <select>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <datao_6> (without init value) has a constant value of 0 in block <terminal>.
|
The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8>
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <cmdatai_7> (without init value) has a constant value of 0 in block <terminal>.
|
FF/Latch <blank_r_3> is unconnected in block <vgai>.
|
|
|
|
|
FF/Latch <blank_r_3> is unconnected in block <vgai>.
|
Unit <chrmemmap>: instances <Mcompar__cmp_ge0000>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
|
|
|
|
|
Unit <chrmemmap>: instances <Mcompar__cmp_ge0000>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_6> are dual, second instance is removed
|
Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_8> are dual, second instance is removed
|
|
|
|
|
Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
|
Unit <terminal>: instances <Mcompar__cmp_gt0000>, <Mcompar__cmp_gt0002> of unit <LPM_COMPARE_12> are equivalent, second instance is removed
|
|
|
|
|
FF/Latch <lincnt_0> is unconnected in block <chrmemmap>.
|
FF/Latch <lincnt_0> is unconnected in block <chrmemmap>.
|
|
|
|
|
| Line 480... |
Line 477... |
|
|
|
|
FF/Latch <inst_Mram_mem9591> is unconnected in block <chrmemmap>.
|
FF/Latch <inst_Mram_mem9591> is unconnected in block <chrmemmap>.
|
|
|
|
|
FF/Latch <pixeldata_0> (without init value) has a constant value of 0 in block <chrmemmap>.
|
FF/Latch <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <pixeldata_7> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <pixeldata_8> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <pixeldata_15> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <scnadr_1> (without init value) has a constant value of 0 in block <chrmemmap>.
|
Due to other FF/Latch trimming, FF/Latch <scnadr_1> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
| Line 504... |
Line 489... |
|
|
|
|
Due to other FF/Latch trimming, FF/Latch <scnadr_3> (without init value) has a constant value of 0 in block <chrmemmap>.
|
Due to other FF/Latch trimming, FF/Latch <scnadr_3> (without init value) has a constant value of 0 in block <chrmemmap>.
|
|
|
|
|
FF/Latch <clkdiv_4> is unconnected in block <testbench>.
|
Unit testbench: 16 multi-source signals are replaced by logic (pull-up yes):
|
|
|
|
|
FF/Latch <clkdiv_5> is unconnected in block <testbench>.
|
Unit chrmemmap: 8 internal tristates are replaced by logic (pull-up yes):
|
|
|
|
|
FF/Latch <clkdiv_6> is unconnected in block <testbench>.
|
FF/Latch <adm3a/display/vgai/blank_r_3> is unconnected in block <testbench>.
|
|
|
|
|
FF/Latch <clkdiv_7> is unconnected in block <testbench>.
|
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/state_FFd13> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
|
|
|
Unit testbench: 16 multi-source signals are replaced by logic (pull-up yes):
|
HDL ADVISOR - A 2-bit shift register was found for signal <cpu/state_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
|
Unit chrmemmap: 8 internal tristates are replaced by logic (pull-up yes):
|
|
|
|
FF/Latch <adm3a/display/vgai/pixel_data_r_15> (without init value) has a constant value of 0 in block <testbench>.
|
HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/vgai/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
|
|
|
FF/Latch <adm3a/display/vgai/blank_r_3> is unconnected in block <testbench>.
|
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/ps2_clk_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
|
|
|
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/display/vgai/blank_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/display/vgai/blank_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
|
|
|
