OpenCores

Rev 2	Rev 7
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`// either use the negative edge, or actually be asynronous logic. //`	`// either use the negative edge, or actually be asynronous logic. //`
`// //`	`// //`
`// A standard read sequence is as follows: //`	`// A standard read sequence is as follows: //`
`// //`	`// //`
`// 1. At the positive clock edge, readmem, readio or readint is asserted. //`	`// 1. At the positive clock edge, readmem, readio or readint is asserted. //`
`// 2. At the positive clock edge (or immediately), the external memory //`	`// 2. At the negative clock edge (or immediately), the external memory //`
`// places data onto the data bus. //`	`// places data onto the data bus. //`
`// 3. At the next positive clock edge, the data is sampled, and the read //`	`// 3. At the next positive clock edge, the data is sampled, and the read //`
`// Signal is deasserted. //`	`// Signal is deasserted. //`
`// //`	`// //`
`// A standard write sequence is as follows: //`	`// A standard write sequence is as follows: //`

Line 35...

//     either use the negative edge, or actually be asynronous logic.         //

//     either use the negative edge, or actually be asynronous logic.         //

//                                                                            //

//                                                                            //

//     A standard read sequence is as follows:                                //

//     A standard read sequence is as follows:                                //

//                                                                            //

//                                                                            //

//     1. At the positive clock edge, readmem, readio or readint is asserted. //

//     1. At the positive clock edge, readmem, readio or readint is asserted. //

//     2. At the positive clock edge (or immediately), the external memory    //

//     2. At the negative clock edge (or immediately), the external memory    //

//        places data onto the data bus.                                      //

//        places data onto the data bus.                                      //

//     3. At the next positive clock edge, the data is sampled, and the read  //

//     3. At the next positive clock edge, the data is sampled, and the read  //

//        Signal is deasserted.                                               //

//        Signal is deasserted.                                               //

//                                                                            //

//                                                                            //

//     A standard write sequence is as follows:                               //

//     A standard write sequence is as follows:                               //

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