| Line 14... |
Line 14... |
// Executes the 8080 instruction set. It is designed to be an internal //
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// Executes the 8080 instruction set. It is designed to be an internal //
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// cell. Each of the I/Os are positive logic, and all signals are //
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// cell. Each of the I/Os are positive logic, and all signals are //
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// constant with the exception of the data bus. The control signals are //
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// constant with the exception of the data bus. The control signals are //
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// fully decoded (unlike the orignal 8080), and features read and write //
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// fully decoded (unlike the orignal 8080), and features read and write //
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// signals for both memory and I/O space. The I/O space is an 8 bit //
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// signals for both memory and I/O space. The I/O space is an 8 bit //
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// address as in the original 8080. //
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// address as in the original 8080. It does NOT echo the lower 8 bits to //
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// the higher 8 bits, as was the practice in some systems. //
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// //
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// //
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// Like the original 8080, the interrupt vectoring is fully external. The //
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// Like the original 8080, the interrupt vectoring is fully external. The //
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// the external controller forces a full instruction onto the data bus. //
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// the external controller forces a full instruction onto the data bus. //
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// The sequence begins with the assertion of interrupt request. The CPU //
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// The sequence begins with the assertion of interrupt request. The CPU //
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// will then assert interrupt acknowledge, then it will run a special //
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// will then assert interrupt acknowledge, then it will run a special //
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// read cycle with readint asserted for each cycle of a possibly //
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// read cycle with inta asserted for each cycle of a possibly //
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// multibyte instruction. This matches the original 8080, which typically //
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// multibyte instruction. This matches the original 8080, which typically //
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// used single byte restart instructions to form a simple interrupt //
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// used single byte restart instructions to form a simple interrupt //
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// controller, but was capable of full vectoring via insertion of a jump, //
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// controller, but was capable of full vectoring via insertion of a jump, //
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// call or similar instruction. //
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// call or similar instruction. //
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// Note that the interrupt vector instruction should branch. This is //
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// because the PC gets changed by the vector instruction, so if it does //
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// not branch, it will have skipped a number of bytes after the interrupt //
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// equivalent to the vector instruction. The only instructions that //
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// should really be used to vector are jmp, rst and call instructions. //
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// Specifically, rst and call instruction compensate for the pc movement //
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// by putting the pc unmodified on the stack. //
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// //
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// //
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// The memory, I/O and interrupt fetches all obey a simple clocking //
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// The memory, I/O and interrupt fetches all obey a simple clocking //
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// sequence as follows. The CPU uses the positive clock edge to assert //
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// sequence as follows. The CPU uses the positive clock edge to assert //
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// and sample signals and data. The external logic theoretically uses the //
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// and sample signals and data. The external logic theoretically uses the //
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// positive edge to check signal assertions and sample data, but it can //
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// negative edge to check signal assertions and sample data, but it can //
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// either use the negative edge, or actually be asynronous logic. //
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// either use the negative edge, or actually be asynronous logic. //
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// The only caution here is that a read device that samples read signals //
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// from the CPU on a postive edge will present data too late, since read //
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// cycles are only one cycle long. This can be fixed with a wait state. //
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// Negative external clockers may also have an issue with the fact that //
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// the net read time is 1/2 cycle, the negative mid cycle clock to the //
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// next positive clock. Again, and perhaps unfortunately, the fix is to //
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// add an external wait state. //
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// //
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// //
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// A standard read sequence is as follows: //
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// A standard read sequence is as follows: //
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// //
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// //
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// 1. At the positive clock edge, readmem, readio or readint is asserted. //
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// 1. At the positive clock edge, readmem, readio or readint is asserted. //
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// 2. At the negative clock edge (or immediately), the external memory //
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// 2. At the negative clock edge (or immediately), the external memory //
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| Line 43... |
Line 58... |
// Signal is deasserted. //
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// Signal is deasserted. //
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// //
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// //
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// A standard write sequence is as follows: //
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// A standard write sequence is as follows: //
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// //
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// //
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// 1. At the positive edge, data is asserted on the data bus. //
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// 1. At the positive edge, data is asserted on the data bus. //
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// 2. At the postive clock edge, writemem or writeio is asserted. //
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// 2. At the next postive clock edge, writemem or writeio is asserted. //
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// 3. At the next positive clock edge, writemem or writeio is deasserted. //
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// 3. At the next positive clock edge, writemem or writeio is deasserted. //
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// 4. At the positive edge, the data is deasserted. //
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// 4. At the next positive edge, the data is deasserted. //
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// //
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// //
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// Dependencies: //
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// Dependencies: //
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// //
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// //
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// Revision: //
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// Revision: //
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// Revision 0.01 - File Created //
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// Revision 0.01 - File Created //
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// Additional Comments: //
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// Additional Comments: //
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// //
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// //
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// Notes: //
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// //
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// 1. Auxiliary carry is not complete. //
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// //
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// 2. inta should take place instead of readmem for each interrupt vector //
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// instruction that is fetched. This behavior matches the original Intel //
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// interrupt controller, and it should not be required to gate readmem OFF //
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// during interrupt cycles. //
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// //
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// CPU states
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// CPU states
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//
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//
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| Line 201... |
Line 207... |
reg [7:0] rdatahold; // single byte read data holding
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reg [7:0] rdatahold; // single byte read data holding
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reg [7:0] rdatahold2; // single byte read data holding
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reg [7:0] rdatahold2; // single byte read data holding
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reg [1:0] popdes; // POP destination code
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reg [1:0] popdes; // POP destination code
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reg [5:0] statesel; // state map selector
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reg [5:0] statesel; // state map selector
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reg [4:0] nextstate; // next state output
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reg [4:0] nextstate; // next state output
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reg eienb; // interrupt enable delay shift reg
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// Register file. Note that 3'b110 (6) is not used, and is the code for a
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// Register file. Note that 3'b110 (6) is not used, and is the code for a
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// memory reference.
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// memory reference.
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reg [7:0] regfil[0:7];
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reg [7:0] regfil[0:7];
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| Line 215... |
Line 222... |
reg auxcar; // auxiliary carry bit
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reg auxcar; // auxiliary carry bit
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reg sign; // sign bit
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reg sign; // sign bit
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reg zero; // zero bit
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reg zero; // zero bit
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reg parity; // parity bit
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reg parity; // parity bit
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reg ei; // interrupt enable
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reg ei; // interrupt enable
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reg intcyc; // in interrupt cycle
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// ALU communication
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// ALU communication
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wire [7:0] alures; // result
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wire [7:0] alures; // result
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reg [7:0] aluopra; // left side operand
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reg [7:0] aluopra; // left side operand
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| Line 243... |
Line 251... |
readmem <= 0; // all signals out false
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readmem <= 0; // all signals out false
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writemem <= 0;
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writemem <= 0;
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readio <= 0;
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readio <= 0;
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writeio <= 0;
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writeio <= 0;
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inta <= 0;
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inta <= 0;
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ei <= 1; // interrupts on on reset, check this
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intcyc <= 0;
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ei <= 1;
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eienb <= 0;
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end else case (state)
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end else case (state)
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`cpus_fetchi: begin // start of instruction fetch
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`cpus_fetchi: begin // start of instruction fetch
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// interrupt is like a normal instruction cycle, except we set the
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// if interrupt request is on, enter interrupt cycle, else exit it now
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// acknowledge for the entire instruction fetch.
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if (intr&&ei) begin
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if (intr && ei) inta <= 1; // interrupt request, set interrupt acknowledge
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else inta <= 0; // clear interrupt acknowledge
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intcyc <= 1; // enter interrupt cycle
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addr <= pc; // place current program count on output
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inta <= 1; // activate interrupt acknowledge
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ei <= 0; // disable interrupts
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end else begin
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intcyc <= 0; // leave interrupt cycle
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readmem <= 1; // activate instruction memory read
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readmem <= 1; // activate instruction memory read
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end
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addr <= pc; // place current program count on output
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if (eienb) ei <=1; // process delayed interrupt enable
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eienb <=0; // reset interrupt enabler
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state <= `cpus_fetchi2; // next state
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state <= `cpus_fetchi2; // next state
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end
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end
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`cpus_fetchi2: begin // complete instruction memory read
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`cpus_fetchi2: begin // complete instruction memory read
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readmem <= 0; // Deactivate instruction memory read
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readmem <= 0; // Deactivate instruction memory read
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inta <= 0; // and interrupt acknowledge
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// We split off the instructions into 4 groups. Most of the 8080
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// We split off the instructions into 4 groups. Most of the 8080
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// instructions are in the MOV and ACC operations class.
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// instructions are in the MOV and ACC operations class.
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case (data[7:6]) // Decode top level
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case (data[7:6]) // Decode top level
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| Line 840... |
Line 862... |
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6'b001101: begin // CALL
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6'b001101: begin // CALL
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raddrhold <= pc+1; // pick up call address
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raddrhold <= pc+1; // pick up call address
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waddrhold <= sp-2; // place address on stack
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waddrhold <= sp-2; // place address on stack
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{ wdatahold2, wdatahold } <= pc+3; // of address after call
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// if interrupt cycle, use current pc, else use address
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// after call
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if (intcyc) { wdatahold2, wdatahold } <= pc;
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else { wdatahold2, wdatahold } <= pc+3;
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sp <= sp-2; // pushdown stack
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sp <= sp-2; // pushdown stack
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statesel <= `mac_call; // finish CALL
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statesel <= `mac_call; // finish CALL
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state <= `cpus_read;
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state <= `cpus_read;
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end
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end
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| Line 925... |
Line 950... |
6'b000111, 6'b001111, 6'b010111, 6'b011111, 6'b100111,
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6'b000111, 6'b001111, 6'b010111, 6'b011111, 6'b100111,
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6'b101111, 6'b110111, 6'b111111: begin // RST
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6'b101111, 6'b110111, 6'b111111: begin // RST
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pc <= data & 8'b00111000; // place restart value in PC
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pc <= data & 8'b00111000; // place restart value in PC
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waddrhold <= sp-2; // place address on stack
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waddrhold <= sp-2; // place address on stack
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// if interrupt cycle, use current pc, else use address
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// after call
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if (intcyc) { wdatahold2, wdatahold } <= pc;
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else { wdatahold2, wdatahold } <= pc+3;
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{ wdatahold2, wdatahold } <= pc+1; // of address after call
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{ wdatahold2, wdatahold } <= pc+1; // of address after call
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sp <= sp-2; // pushdown stack
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sp <= sp-2; // pushdown stack
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statesel <= `mac_writedbyte; // finish RST
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statesel <= `mac_writedbyte; // finish RST
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state <= `cpus_write; // write to stack
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state <= `cpus_write; // write to stack
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| Line 1038... |
Line 1067... |
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`cpus_read: begin
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`cpus_read: begin
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addr <= raddrhold; // place address on output
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addr <= raddrhold; // place address on output
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raddrhold <= raddrhold+1; // next address
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raddrhold <= raddrhold+1; // next address
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readmem <= 1; // activate instruction memory read
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if (intcyc) inta <= 1; // activate interrupt acknowledge
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else readmem <= 1; // activate instruction memory read
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state <= `cpus_read2; // next state
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state <= `cpus_read2; // next state
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end
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end
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`cpus_read2: begin // continue read #2
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`cpus_read2: begin // continue read #2
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| Line 1050... |
Line 1080... |
if (!waitr) begin // no wait selected, otherwise cycle
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if (!waitr) begin // no wait selected, otherwise cycle
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rdatahold2 <= rdatahold; // shift data
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rdatahold2 <= rdatahold; // shift data
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rdatahold <= data; // read new data
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rdatahold <= data; // read new data
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readmem <= 0; // deactivate instruction memory read
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readmem <= 0; // deactivate instruction memory read
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inta <= 0; // deactivate interrupt acknowledge
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state <= nextstate; // get next macro state
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state <= nextstate; // get next macro state
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statesel <= statesel+1; // and index next in macro
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statesel <= statesel+1; // and index next in macro
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end
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end
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| Line 1138... |
Line 1169... |
|
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end
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end
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`cpus_halt: begin // Halt waiting for interrupt
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`cpus_halt: begin // Halt waiting for interrupt
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|
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// nothing to do, we leave the state at halt, which will cause it to
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// If there is an interrupt request and interrupts are enabled, then we
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// be executed continually until we exit.
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// can leave halt. Otherwise we stay here.
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if (intr&&ei) state <= `cpus_fetchi; // Fetch next instruction
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else state <= `cpus_halt;
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end
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end
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`cpus_movtr: begin // move to register
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`cpus_movtr: begin // move to register
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|
