| Line 6... |
Line 6... |
// / /\/ /
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 8.2.02i
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// \ \ \/ Version : 8.2.02i
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// \ \ Application : ISE
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// \ \ Application : ISE
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// / / Filename : cpu_tbw.ant
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// / / Filename : cpu_tbw.ant
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// /___/ /\ Timestamp : Fri Oct 20 21:19:57 2006
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// /___/ /\ Timestamp : Sat Oct 28 09:12:59 2006
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// \ \ / \
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// \ \ / \
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// \___\/\___\
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// \___\/\___\
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//
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//
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//Command:
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//Command:
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//Design Name: cpu_tbw
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//Design Name: cpu_tbw
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| Line 18... |
Line 18... |
//
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//
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module cpu_tbw;
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module cpu_tbw;
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wire [15:0] addr;
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wire [15:0] addr;
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reg [7:0] data$inout$reg = 8'bZZZZZZZZ;
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reg [7:0] data$inout$reg = 8'bZ1Z00000;
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wire [7:0] data = data$inout$reg;
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wire [7:0] data = data$inout$reg;
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wire readmem;
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wire readmem;
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wire writemem;
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wire writemem;
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wire readio;
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wire readio;
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wire writeio;
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wire writeio;
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wire intr;
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wire intr;
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wire inta;
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wire inta;
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reg waitr = 1'b0;
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reg waitr = 1'b0;
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reg reset = 1'b1;
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wire [2:0] r;
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wire [2:0] g;
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wire [2:0] b;
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wire hsync_n;
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wire vsync_n;
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reg reset = 1'b0;
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reg clock = 1'b0;
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reg clock = 1'b0;
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parameter PERIOD = 200;
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parameter PERIOD = 200;
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parameter real DUTY_CYCLE = 0.5;
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parameter real DUTY_CYCLE = 0.5;
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parameter OFFSET = 0;
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parameter OFFSET = 0;
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.readio(readio),
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.readio(readio),
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.writeio(writeio),
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.writeio(writeio),
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.intr(intr),
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.intr(intr),
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.inta(inta),
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.inta(inta),
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.waitr(waitr),
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.waitr(waitr),
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.r(r),
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.g(g),
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.b(b),
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.hsync_n(hsync_n),
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.vsync_n(vsync_n),
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.reset(reset),
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.reset(reset),
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.clock(clock));
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.clock(clock));
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integer TX_FILE = 0;
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integer TX_FILE = 0;
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integer TX_ERROR = 0;
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integer TX_ERROR = 0;
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| Line 70... |
Line 80... |
ANNOTATE_writemem;
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ANNOTATE_writemem;
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ANNOTATE_readio;
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ANNOTATE_readio;
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ANNOTATE_writeio;
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ANNOTATE_writeio;
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ANNOTATE_intr;
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ANNOTATE_intr;
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ANNOTATE_inta;
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ANNOTATE_inta;
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ANNOTATE_r;
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ANNOTATE_g;
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ANNOTATE_b;
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ANNOTATE_hsync_n;
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ANNOTATE_vsync_n;
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#OFFSET;
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#OFFSET;
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forever begin
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forever begin
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#115;
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#115;
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ANNOTATE_addr;
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ANNOTATE_addr;
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ANNOTATE_readmem;
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ANNOTATE_readmem;
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ANNOTATE_writemem;
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ANNOTATE_writemem;
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ANNOTATE_readio;
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ANNOTATE_readio;
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ANNOTATE_writeio;
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ANNOTATE_writeio;
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ANNOTATE_intr;
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ANNOTATE_intr;
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ANNOTATE_inta;
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ANNOTATE_inta;
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ANNOTATE_r;
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ANNOTATE_g;
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ANNOTATE_b;
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ANNOTATE_hsync_n;
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ANNOTATE_vsync_n;
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#85;
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#85;
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end
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end
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end
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end
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initial begin // Open the annotations file...
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initial begin // Open the annotations file...
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TX_FILE = $fopen("C:\\Xilinx\\ISEexamples\\cpu8080\\cpu_tbw.ano");
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TX_FILE = $fopen("C:\\Xilinx\\ISEexamples\\cpu8080\\cpu_tbw.ano");
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#10200 // Final time: 10200 ns
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#100200 // Final time: 100200 ns
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$display("Success! Annotation Simulation Complete.");
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$display("Success! Annotation Simulation Complete.");
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$fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
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$fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
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$fclose(TX_FILE);
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$fclose(TX_FILE);
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$finish;
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$finish;
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end
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end
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|
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initial begin
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initial begin
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// ------------- Current Time: 485ns
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// ------------- Current Time: 85ns
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#485;
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#85;
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reset = 1'b1;
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reset = 1'b0;
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reset = 1'b0;
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// -------------------------------------
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// -------------------------------------
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end
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end
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|
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task ANNOTATE_addr;
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task ANNOTATE_addr;
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| Line 156... |
Line 177... |
$fflush(TX_FILE);
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$fflush(TX_FILE);
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TX_ERROR = TX_ERROR + 1;
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TX_ERROR = TX_ERROR + 1;
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end
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end
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endtask
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endtask
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task ANNOTATE_r;
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#0 begin
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$fdisplay(TX_FILE, "Annotate[%d,r,%b]", $time, r);
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$fflush(TX_FILE);
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TX_ERROR = TX_ERROR + 1;
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end
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endtask
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task ANNOTATE_g;
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#0 begin
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$fdisplay(TX_FILE, "Annotate[%d,g,%b]", $time, g);
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$fflush(TX_FILE);
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TX_ERROR = TX_ERROR + 1;
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end
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endtask
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task ANNOTATE_b;
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#0 begin
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$fdisplay(TX_FILE, "Annotate[%d,b,%b]", $time, b);
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$fflush(TX_FILE);
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TX_ERROR = TX_ERROR + 1;
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end
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endtask
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task ANNOTATE_hsync_n;
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#0 begin
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$fdisplay(TX_FILE, "Annotate[%d,hsync_n,%b]", $time, hsync_n);
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$fflush(TX_FILE);
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TX_ERROR = TX_ERROR + 1;
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end
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endtask
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task ANNOTATE_vsync_n;
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#0 begin
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$fdisplay(TX_FILE, "Annotate[%d,vsync_n,%b]", $time, vsync_n);
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$fflush(TX_FILE);
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TX_ERROR = TX_ERROR + 1;
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end
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endtask
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endmodule
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endmodule
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