URL
https://opencores.org/ocsvn/cpu8080/cpu8080/trunk
[/] [cpu8080/] [trunk/] [project/] [readme.txt] - Diff between revs 5 and 9
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 5 |
Rev 9 |
Line 13... |
Line 13... |
Description
|
Description
|
|
|
This is an 8080 core I created as a project to get to know Verilog.
|
This is an 8080 core I created as a project to get to know Verilog.
|
|
|
The 8080 was the second in the series 8008->8080->Z80. It was the first
|
The 8080 was the second in the series 8008->8080->Z80. It was the first
|
commercially available single chip CPU (disregarding the required clock and *
|
commercially available single chip CPU (disregarding the required clock and
|
demultiplexor chips). Besides being an interesting project, it also can serve as
|
demultiplexor chips). Besides being an interesting project, it also can serve as
|
a very compact core, suitable for a supervisor role on an FPGA with other
|
a very compact core, suitable for a supervisor role on an FPGA with other
|
blocks. It has extensive support, all freely available, including assemblers,
|
blocks. It has extensive support, all freely available, including assemblers,
|
compilers, an operating system (CP/M).
|
compilers, an operating system (CP/M).
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.