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Line 3... |
Loading device for application Rf_Device from file '3s1000.nph' in environment
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Loading device for application Rf_Device from file '3s1000.nph' in environment
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C:\Xilinx.
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C:\Xilinx.
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"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
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"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
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Opened constraints file testbench.pcf.
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Opened constraints file testbench.pcf.
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Wed Nov 01 08:51:32 2006
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Sat Nov 11 00:55:41 2006
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C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullNone -g M0Pin:PullNone -g M1Pin:PullNone -g M2Pin:PullNone -g ProgPin:PullNone -g DonePin:PullNone -g TckPin:PullNone -g TdiPin:PullNone -g TdoPin:PullNone -g TmsPin:PullNone -g UnusedPin:PullNone -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No testbench.ncd
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C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullNone -g M0Pin:PullNone -g M1Pin:PullNone -g M2Pin:PullNone -g ProgPin:PullNone -g DonePin:PullNone -g TckPin:PullNone -g TdiPin:PullNone -g TdoPin:PullNone -g TmsPin:PullNone -g UnusedPin:PullNone -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No testbench.ncd
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Summary of Bitgen Options:
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Summary of Bitgen Options:
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+----------------------+----------------------+
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+----------------------+----------------------+
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| Line 95... |
Line 95... |
+----------------------+----------------------+
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+----------------------+----------------------+
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* Default setting.
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* Default setting.
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** The specified setting matches the default setting.
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** The specified setting matches the default setting.
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Running DRC.
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Running DRC.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
|
sourced by a combinatorial pin. This is not good design practice. Use the CE
|
pin to control the loading of data into the flip-flop.
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pin to control the loading of data into the flip-flop.
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DRC detected 0 errors and 4 warnings.
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DRC detected 0 errors and 4 warnings.
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Creating bit map...
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Creating bit map...
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Saving bit stream in "testbench.bit".
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Saving bit stream in "testbench.bit".
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