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[/] [cpu8080/] [trunk/] [project/] [testbench.drc] - Diff between revs 11 and 18

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Rev 11 Rev 18
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   pin to control the loading of data into the flip-flop.
 
   pin to control the loading of data into the flip-flop.
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   pin to control the loading of data into the flip-flop.
 
   pin to control the loading of data into the flip-flop.
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   pin to control the loading of data into the flip-flop.
 
   pin to control the loading of data into the flip-flop.
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   sourced by a combinatorial pin. This is not good design practice. Use the CE
 
   pin to control the loading of data into the flip-flop.
 
   pin to control the loading of data into the flip-flop.
 
DRC detected 0 errors and 4 warnings.
 
DRC detected 0 errors and 4 warnings.

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